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| D R A FT D R A FT D R A FT D R A FT D R A FT LPC2917/19 ARM9 microcontroller with CAN and LIN Rev. 1.01 -- 15 November 2007 D D R A FT D D R A FT D R A FT D D R A R A FT D R A R A FT D R A FT D R A F R A FT D R R D Preliminary data sheet FT D R A FT FT A FT 1. Introduction 1.1 About this document D This document lists detailed information about the LPC2917/19 device. It focuses on factual information like pinning, characteristics etc. Short descriptions are used to outline the concept of the features and functions. More details and background on developing applications for this device are given in the LPC2917/19 User Manual (see Ref. 1). No explicit references are made to the User Manual. D R A FT D R A 1.2 Intended audience This document is written for engineers evaluating and/or developing systems, hardand/or software for the LPC2917/19. Some basic knowledge of ARM processors and architecture and ARM968E-S in particular is assumed (see Ref. 2). 2. General description 2.1 Architectural overview The LPC2917/19 consists of: * An ARM968E-S processor with real-time emulation support * An AMBA multi-layer Advanced High-performance Bus (AHB) for interfacing to the on-chip memory controllers * Two DTL buses (a universal NXP interface) for interfacing to the interrupt controller and the Power, Clock and Reset Control cluster (also called subsystem) * Three VLSI Peripheral Buses (VPB - a compatible superset of ARM's AMBA advanced peripheral bus) for connection to on-chip peripherals clustered in subsystems. The LPC2917/19 configures the ARM968E-S processor in little-endian byte order. All peripherals run at their own clock frequency to optimize the total system power consumption. The AHB2VPB bridge used in the subsystems contains a write-ahead buffer one transaction deep. This implies that when the ARM968E-S issues a buffered write action to a register located on the VPB side of the bridge, it continues even though the actual write may not yet have taken place. Completion of a second write to the same subsystem will not be executed until the first write is finished. D R A FT NXP Semiconductors LPC2917/19 FT FT FT D D R R A A A FT FT FT D D R A FT D R R A FT D D D R A D R ARM9 microcontroller with CAN and LIN A D R A D R A D D R A FT A FT D R FT R 2.2 ARM968E-S processor D R The ARM968E-S is a general purpose 32-bit RISC processor, which offers high performance and very low power consumption. The ARM architecture is based on Reduced Instruction Set Computer (RISC) principles, and the instruction set and related decode mechanism are much simpler than those of micro-programmed Complex Instruction Set Computers (CISC). This simplicity results in a high instruction throughput and impressive real-time interrupt response from a small and cost-effective controller core. D R A FT R A FT R A F D R A FT D A FT D R A R A FT D Amongst the most compelling features of the ARM968E-S are: * Separate directly connected instruction and data Tightly Coupled Memory (TCM) interfaces * Write buffers for the AHB and TCM buses * Enhanced 16 x 32 multiplier capable of single-cycle MAC operations and 16-bit fixedpoint DSP instructions to accelerate signal-processing algorithms and applications. Pipeline techniques are employed so that all parts of the processing and memory systems can operate continuously. The ARM968E-S is based on the ARMv5TE five-stage pipeline architecture. Typically, in a three-stage pipeline architecture, while one instruction is being executed its successor is being decoded and a third instruction is being fetched from memory. In the five-stage pipeline additional stages are added for memory access and write-back cycles. The ARM968E-S processor also employs a unique architectural strategy known as THUMB, which makes it ideally suited to high-volume applications with memory restrictions or to applications where code density is an issue. The key idea behind THUMB is that of a super-reduced instruction set. Essentially, the ARM968E-S processor has two instruction sets: * Standard 32-bit ARMv5TE set * 16-bit THUMB set The THUMB set's 16-bit instruction length allows it to approach twice the density of standard ARM code while retaining most of the ARM's performance advantage over a traditional 16-bit controller using 16-bit registers. This is possible because THUMB code operates on the same 32-bit register set as ARM code. THUMB code can provide up to 65 % of the code size of ARM, and 160 % of the performance of an equivalent ARM controller connected to a 16-bit memory system. The ARM968E-S processor is described in detail in the ARM968E-S data sheet Ref. 2. 2.3 On-chip flash memory system The LPC2917/19 includes a 512 kB or 768 kB flash memory system. This memory can be used for both code and data storage. Programming of the flash memory can be accomplished in several ways. It may be programmed in-system via a serial port; e.g. CAN. LPC2917_19_1 (c) NXP B.V. 2007. All rights reserved. Preliminary data sheet Rev. 1.01 -- 15 November 2007 2 of 68 D R A FT NXP Semiconductors LPC2917/19 FT FT FT D D R R A A A FT FT FT D D R A FT D R R A FT D D D R A D R ARM9 microcontroller with CAN and LIN A D R A D R A D D R A FT A FT D R FT R 2.4 On-chip static RAM D R In addition to the two 16 kB TCMs the LPC2917/19 includes two static RAM memories: one of 32 kB and one of 16 kB. Both may be used for code and/or data storage. Each internal SRAM has its own controller, so both memories can be accessed simultaneously from different AHB system bus layers. D R A FT D R A FT R A F D R A FT D FT D R A A FT 3. Features 3.1 General ARM968E-S processor at 80 MHz maximum Multi-layer AHB system bus at 80 MHz with three separate layers On-chip memory: Two Tightly Coupled Memories (TCM), 16 kB Instruction (ITCM), 16 kB Data TCM (DTCM) Two separate internal Static RAM (SRAM) instances; 32 kB SRAM and 16 kB SRAM Up to 768 kB flash-program memory Two-channel CAN controller supporting Full-CAN and extensive message filtering Two LIN master controllers with full hardware support for LIN communication Two 550 UARTs with 16-byte Tx and Rx FIFO depths Three full-duplex Q-SPIs with four slave-select lines; 16 bits wide; 8 locations deep; Tx FIFO and Rx FIFO Four 32-bit timers each containing four capture-and-compare registers linked to I/Os 32-bit watchdog with timer change protection, running on safe clock. Up to 108 general-purpose I/O pins with programmable pull-up, pull-down or bus keeper Vectored Interrupt Controller (VIC) with 16 priority levels Two 8-channel 10-bit ADCs provide a total of up to 16 analog inputs, with conversion times as low as 2.44 s per channel. Each channel provides a compare function to minimize interrupts Up to 24 level-sensitive external interrupt pins, including CAN and LIN wake- up features External Static Memory Controller (SMC) with eight memory banks; up to 32-bit data bus; up to 24-bit address bus Processor wake-up from power-down via external interrupt pins; CAN or LIN activity Flexible Reset Generator Unit (RGU) able to control resets of individual modules Flexible Clock-Generation Unit (CGU) able to control clock frequency of individual modules On-chip very low-power ring oscillator; fixed frequency of 0.4 MHz; always on to provide a Safe_Clock source for system monitoring On-chip crystal oscillator with operating range from 10 MHz to 50 MHz - max. PLL input 15 MHz On-chip PLL allows CPU operation up to a maximum CPU rate of 80 MHz Generation of up to 10 base clocks Seven fractional dividers LPC2917_19_1 (c) NXP B.V. 2007. All rights reserved. R A Preliminary data sheet Rev. 1.01 -- 15 November 2007 3 of 68 D R A FT NXP Semiconductors LPC2917/19 FT FT FT D D R R A A A FT FT FT D D R A FT D R D R R A FT D D R A D R ARM9 microcontroller with CAN and LIN A Highly configurable system Power Management Unit (PMU), clock control of individual modules allows minimization of system operating power consumption in any configuration Standard ARM test and debug interface with real-time in-circuit emulator Boundary-scan test supported Dual power supply: CPU operating voltage: 1.8 V 5% I/O operating voltage: 2.7 V to 3.6 V; inputs tolerant up to 5.5 V 144-pin LQFP package -40 C to 85 C ambient operating temperature range R A FT D R A FT D R A D R A D A FT D R D R A FT A FT D R FT D R A F R A FT D A FT D R A D R 4. Ordering information Table 1. Ordering information Package Name LPC2917FBD144 LPC2919FBD144 LQFP144 LQFP144 Description Version plastic low profile quad flat package; 144 leads; body 20 x 20 x 1.4 mm, pin SOT486-1 pitch 0.5 mm plastic low profile quad flat package; 144 leads; body 20 x 20 x 1.4 mm, pin SOT486-1 pitch 0.5 mm Type number 4.1 Ordering options Table 2. Part options Flash memory (kB) 512 768 RAM (kB) 80 (incl TCMs) 80 (incl TCMs) SMC 32-bit 32-bit LIN 2.0 2 2 Package LQFP144 LQFP144 Type number LPC2917FBD144 LPC2919FBD144 LPC2917_19_1 (c) NXP B.V. 2007. All rights reserved. Preliminary data sheet Rev. 1.01 -- 15 November 2007 4 of 68 D R A FT NXP Semiconductors LPC2917/19 FT FT FT D D R R A A A FT FT FT D D R A FT D R R A FT D D D R A D R ARM9 microcontroller with CAN and LIN A D R A D R A D D R A FT A FT D R FT R 5. Block diagram D R R A FT D R R A F D R A FT A FT A FT D R A D FT LPC2917/19 ITCM 16 Kb ARM968E-S DTCM 16 Kb D R A s AH B2D TL Bridge m IEEE 1149.1 JTAG TEST and DEBUG INTERFACE Vectored Interrupt Controller (VIC) s s Embedded FLASH Memory 512/768 Kb s FLASH Memory Controller (FMC) s External Static Memory Controller (SMC) Embedded SRAM Memory 16 Kb SRAM Controller #1 Modulation and Sampling Control Subsystem Timer 0, 1 (MTMR) AH B2VPB Bridge Embedded SRAM Memory 32 Kb s s SRAM Controller #0 General Subsystem Chip Feature ID (CFID) s A HB2VP B Bridge PWM 0, 1, 2, 3 ADC 1, 2 System Control Unit (SCU) Event Router (ER) CAN Controller 0, 1 AH B2VPB Bridge GLOBAL ACCEPTANCE FILTER 2 Kbyte Static RAM s Peripheral Subsystem General Purpose IO (GPIO) 0, 1, 2, 3 Timer (TMR) 0, 1, 2, 3 SPI 0, 1, 2 UART 0, 1 Watchdog Timer (WDT) LIN MASTER 0/1 s AH B2VPB B ridge Power Clock Reset Control Subsystem Clock Generation Unit (CGU) s A HB2D T L Bridge Reset Generation Unit (RGU) Power Management Unit (PMU) Multi-layer AHB system bus m = master port s = slave port Fig 1. LPC2917/19 block diagram LPC2917_19_1 (c) NXP B.V. 2007. All rights reserved. Preliminary data sheet Rev. 1.01 -- 15 November 2007 5 of 68 D R A FT NXP Semiconductors LPC2917/19 FT FT FT D D R R A A A FT FT FT D D R A FT D R R A FT D D D R A D R ARM9 microcontroller with CAN and LIN A D R A D R A D D R A FT A FT D R FT R 6. Pinning information 6.1 Pinning 144 109 D R R A FT D R R A F D R A FT A FT A FT D R A D FT D R A 1 108 LPC2917FBD144 LPC2919FBD144 36 37 72 73 144PINS Fig 2. Pin configuration for SOT486-1 (LQFP144) 6.2 Pin description 6.2.1 General description The LPC2917/19 has up to four ports: two of 32 pins each, one of 28 pins and one of 16 pins. The pin to which each function is assigned is controlled by the SFSP registers in the SCU. The functions combined on each port pin are shown in the pin description tables in this section. 6.2.2 LQFP144 pin assignment Table 3. Symbol TDO P2.21 P0.24 P0.25 P0.26 P0.27 P0.28 P0.29 VDD(IO) P2.22 P2.23 P3.6 P3.7 P0.30 P0.31 LPC2917_19_1 LQFP144 pin assignment Pin 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Description Function 0 (default) GPIO 2, pin 21 GPIO 0, pin 24 GPIO 0, pin 25 GPIO 0, pin 26 GPIO 0, pin 27 GPIO 0, pin 28 GPIO 0, pin 29 3.3 V power supply for I/O GPIO 2, pin 22 GPIO 2, pin 23 GPIO 3, pin 6 GPIO 3, pin 7 GPIO 0, pin 30 GPIO 0, pin 31 SPI0 SCS3 SPI2 SCS1 PWM2 CAP2 PWM3 CAP0 PWM1 MAT0 PWM1 MAT1 TIMER0 CAP2 TIMER0 CAP3 EXTBUS D20 EXTBUS D21 LIN1 TxD LIN1 RxD TIMER0 MAT2 TIMER0 MAT3 (c) NXP B.V. 2007. All rights reserved. Function 1 UART1 TxD UART1 RxD - Function 2 PWM2 CAP1 CAN1 TxD CAN1 RxD TIMER0 CAP0 TIMER0 CAP1 Function 3 EXTBUS D19 SPI2 SCS0 SPI2 SDO SPI2 SDI SPI2 SCK TIMER0 MAT0 TIMER0 MAT1 IEEE 1149.1 test data out Preliminary data sheet Rev. 1.01 -- 15 November 2007 6 of 68 D R A FT NXP Semiconductors LPC2917/19 FT FT FT D D R R A A A FT FT FT D D R A FT D R R A FT D D D R A D R ARM9 microcontroller with CAN and LIN A D R A D R A D D R A FT A FT D R FT R Table 3. Symbol P2.24 P2.25 VDD(CORE) VSS(CORE) P1.31 VSS(IO) P1.30 P3.8 P3.9 P1.29 P1.28 P2.26 P2.27 P1.27 P1.26 VDD(IO) P1.25 P1.24 P1.23 P1.22 TMS TCK P1.21 P1.20 P1.19 P1.18 P1.17 VSS(IO) P1.16 P2.0 P2.1 P3.10 P3.11 P1.15 P1.14 P1.13 P1.12 LPC2917_19_1 LQFP144 pin assignment ...continued Pin 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 Description Function 0 (default) GPIO 2, pin 24 GPIO 2, pin 25 ground for digital core GPIO 1, pin 31 ground for I/O GPIO 1, pin 30 GPIO 3, pin 8 GPIO 3, pin 9 GPIO 1, pin 29 GPIO 1, pin 28 GPIO 2, pin 26 GPIO 2, pin 27 GPIO 1, pin 27 GPIO 1, pin 26 GPIO 1, pin 25 GPIO 1, pin 24 GPIO 1, pin 23 GPIO 1, pin 22 IEEE 1149.1 test clock GPIO 1, pin 21 GPIO 1, pin 20 GPIO 1, pin 19 GPIO 1, pin 18 GPIO 1, pin 17 ground for I/O GPIO 1, pin 16 GPIO 2, pin 0 GPIO 2, pin 1 GPIO 3, pin 10 GPIO 3, pin 11 GPIO 1, pin 15 GPIO 1, pin 14 GPIO 1, pin 13 GPIO 1, pin 12 TIMER2 CAP2 TIMER2 MAT0 TIMER2 MAT1 SPI2 SDI SPI2 SCK TIMER2 CAP1 TIMER2 CAP0 EXTINT3 EXTINT2 SPI0 SCK PWM TRAP3 PWM TRAP2 PWM1 MAT4 PWM1 MAT5 SPI0 SCS0 SPI0 SCS3 TIMER3 CAP3 TIMER3 CAP2 TIMER3 CAP1 TIMER3 CAP0 TIMER2 CAP3 TIMER1 CAP3, MSCSS PAUSE SPI0 SCS1 SPI0 SCS2 SPI0 SDO SPI0 SDI TIMER0 CAP0 SPI2 SCS0 SPI2 SDO TIMER1 CAP0, EXT START TIMER0 MAT0 PWM1 MAT2 PWM1 MAT3 PWM TRAP0 TIMER0 CAP1 TIMER0 MAT1 Function 1 Function 2 PWM3 CAP1 PWM3 CAP2 D R Function 3 EXTBUS D22 EXTBUS D23 R A FT D R R A F D R A FT A FT A FT D R A D FT 1.8 V power supply for digital core EXTINT5 EXTINT4 PWM3 MAT5 PWM3 MAT4 EXTINT6 EXTINT7 PWM3 MAT3 PWM3 MAT2 PWM3 MAT1 PWM3 MAT0 EXTBUS CS5 EXTBUS CS4 D R A TIMER1 CAP1, ADC1 PWM TRAP1 EXT START TIMER0 CAP2 TIMER0 CAP3 TIMER0 MAT2 TIMER0 MAT3 TIMER1 CAP2, ADC2 PWM TRAP2 EXT START PWM2 MAT0 PWM1 MAT0 PWM0 MAT0 UART0 RxD UART0 TxD PWM TRAP3 - 3.3 V power supply for I/O IEEE 1149.1 test mode select, pulled up internally. EXTBUS D7 EXTBUS D6 EXTBUS D5 EXTBUS D4 EXTBUS D3 EXTBUS D2 EXTBUS D8 EXTBUS D9 EXTBUS D1 EXTBUS D0 EXTBUS WEN EXTBUS OEN (c) NXP B.V. 2007. All rights reserved. Preliminary data sheet Rev. 1.01 -- 15 November 2007 7 of 68 D R A FT NXP Semiconductors LPC2917/19 FT FT FT D D R R A A A FT FT FT D D R A FT D R R A FT D D D R A D R ARM9 microcontroller with CAN and LIN A D R A D R A D D R A FT A FT D R FT R Table 3. Symbol VDD(IO) P2.2 P2.3 P1.11 P1.10 P3.12 VSS(CORE) VDD(CORE) P3.13 P2.4 P2.5 P1.9 VSS(IO) P1.8 P1.7 P1.6 P2.6 P1.5 P1.4 TRSTN RSTN VSS(OSC) LQFP144 pin assignment ...continued Pin 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 Description Function 0 (default) GPIO 2, pin 2 GPIO 2, pin 3 GPIO 1, pin 11 GPIO 1, pin 10 GPIO 3, pin 12 ground for digital core 1.8 V power supply for digital core GPIO 3, pin 13 GPIO 2, pin 4 GPIO 2, pin 5 GPIO 1, pin 9 ground for I/O GPIO 1, pin 8 GPIO 1, pin 7 GPIO 1, pin 6 GPIO 2, pin 6 GPIO 1, pin 5 GPIO 1, pin 4 SPI1 SCS0 SPI1 SCS3 SPI1 SCS2 TIMER1 MAT2 SPI1 SCS1 SPI2 SCS2 LIN1 TxD UART1 RxD UART1 TxD EXTINT2 PWM3 MAT5 PWM3 MAT4 SPI1 SDO TIMER1 MAT0 TIMER1 MAT1 SPI1 SDO EXTINT5 EXTINT0 EXTINT1 LIN1 RxD Function 1 TIMER2 MAT2 TIMER2 MAT3 SPI1 SCK SPI1 SDI SPI1 SCS0 Function 2 PWM TRAP1 PWM TRAP0 EXTINT4 3.3 V power supply for I/O D R Function 3 EXTBUS D10 EXTBUS D11 EXTBUS CS3 EXTBUS CS2 - EXTBUS D12 EXTBUS D13 EXTBUS CS1 EXTBUS CS0 EXTBUS A7 EXTBUS A6 EXTBUS D14 EXTBUS A5 EXTBUS A4 R A FT D R R A F D R A FT A FT A FT D R A D FT D R A IEEE 1149.1 test reset NOT; active LOW; pulled up internally asynchronous device reset; active LOW; pulled up internally ground for oscillator crystal out for oscillator crystal in for oscillator 1.8 V supply for oscillator ground for PLL GPIO 2, pin 7 GPIO 3, pin 14 GPIO 3, pin 15 GPIO 2, pin 8 GPIO 2, pin 9 GPIO 1, pin 3 GPIO 1, pin 2 GPIO 1, pin 1 ground for digital core 1.8 V power supply for digital core GPIO 1, pin 0 GPIO 2, pin 10 GPIO 2, pin 11 EXTINT0 PWM3 MAT0 PWM0 MAT2 PWM0 MAT3 EXTBUS A0 SPI0 SCS0 SPI0 SCK (c) NXP B.V. 2007. All rights reserved. XOUT_OSC XIN_OSC VDD(OSC) VSS(PLL) P2.7 P3.14 P3.15 VDD(IO) P2.8 P2.9 P1.3 P1.2 P1.1 VSS(CORE) VDD(CORE) P1.0 P2.10 P2.11 LPC2917_19_1 TIMER1 MAT3 SPI1 SDI SPI1 SCK SPI2 SCS1 SPI2 SCS3 EXTINT1 EXTINT3 EXTINT6 EXTINT7 PWM0 MAT0 PWM0 MAT1 PWM3 MAT3 PWM3 MAT2 PWM3 MAT1 EXTBUS D15 CAN0 TxD CAN0 RxD SPI0 SCS2 SPI0 SCS1 EXTBUS A3 EXTBUS A2 EXTBUS A1 3.3 V power supply for I/O Preliminary data sheet Rev. 1.01 -- 15 November 2007 8 of 68 D R A FT NXP Semiconductors LPC2917/19 FT FT FT D D R R A A A FT FT FT D D R A FT D R R A FT D D D R A D R ARM9 microcontroller with CAN and LIN A D R A D R A D D R A FT A FT D R FT R Table 3. Symbol P0.0 VSS(IO) P0.1 P0.2 P0.3 P3.0 P3.1 P2.12 P2.13 P0.4 P0.5 VDD(IO) P0.6 P0.7 VDD(A3V3) JTAGSEL NC VREFP VREFN P0.8 P0.9 P0.10 P0.11 P2.14 P2.15 P3.2 VSS(IO) P3.3 P0.12 P0.13 P0.14 P0.15 P0.16 P0.17 VDD(CORE) VSS(CORE) P2.16 P2.17 VDD(IO) LPC2917_19_1 LQFP144 pin assignment ...continued Pin 93 94 95 96 97 98 99 100 101 102 103 104 105 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 121 122 123 124 125 126 127 128 129 130 131 Description Function 0 (default) GPIO 0, pin 0 ground for I/O GPIO 0, pin 1 GPIO 0, pin 2 GPIO 0, pin 3 GPIO 3, pin 0 GPIO 3, pin 1 GPIO 2, pin 12 GPIO 2, pin 13 GPIO 0, pin 4 GPIO 0, pin 5 GPIO 0, pin 6 GPIO 0, pin 7 CAN0 RxD PWM0 MAT0 PWM0 MAT1 PWM2 MAT0 PWM2 MAT1 PWM0 MAT4 PWM0 MAT5 PWM0 MAT2 PWM0 MAT3 PWM0 MAT4 PWM0 MAT5 Function 1 Function 2 CAN0 TxD D R Function 3 EXTBUS D24 EXTBUS D25 EXTBUS D26 EXTBUS D27 EXTBUS CS6 EXTBUS CS7 SPI0 SDI SPI0 SDO EXTBUS D28 EXTBUS D29 EXTBUS D30 EXTBUS D31 R A FT D R R A F D R A FT A FT A FT D R A D FT D R A 3.3 V power supply for I/O 3.3 V power supply for AD Converters TAP controller select input; LOW-level selects the ARM debug mode; HIGH-level selects boundary scan and flash programming; pulled up internally HIGH reference for AD Converters LOW reference for AD Converters GPIO 0, pin 8 GPIO 0, pin 9 GPIO 0, pin 10 GPIO 0, pin 11 GPIO 2, pin 14 GPIO 2, pin 15 GPIO 3, pin 2 ground for I/O GPIO 3, pin 3 GPIO 0, pin 12 GPIO 0, pin 13 GPIO 0, pin 14 GPIO 0, pin 15 GPIO 0, pin 16 GPIO 0, pin 17 ground for digital core GPIO 2, pin 16 GPIO 2, pin 17 UART1 TxD UART1 RxD PWM0 CAP2 PWM1 CAP0 EXTBUS BLS2 EXTBUS BLS3 TIMER3 MAT1 ADC1 IN4 ADC1 IN5 ADC1 IN6 ADC1 IN7 ADC2 IN0 ADC2 IN1 PWM2 MAT3 PWM1 MAT2 PWM1 MAT3 PWM1 MAT4 PWM1 MAT5 UART0 TXD UART0 RXD EXTBUS A10 EXTBUS A11 EXTBUS A12 EXTBUS A13 EXTBUS A22 EXTBUS A23 ADC1 IN0 ADC1 IN1 ADC1 IN2 ADC1 IN3 TIMER3 MAT0 LIN0 TxD LIN0 RxD PWM1 MAT0 PWM1 MAT1 PWM0 CAP0 PWM0 CAP1 PWM2 MAT2 EXTBUS A20 EXTBUS A21 EXTBUS A8 EXTBUS A9 EXTBUS BLS0 EXTBUS BLS1 - 1.8 V power supply for digital core 3.3 V power supply for I/O (c) NXP B.V. 2007. All rights reserved. Preliminary data sheet Rev. 1.01 -- 15 November 2007 9 of 68 D R A FT NXP Semiconductors LPC2917/19 FT FT FT D D R R A A A FT FT FT D D R A FT D R R A FT D D D R A D R ARM9 microcontroller with CAN and LIN A D R A D R A D D R A FT A FT D R FT R Table 3. Symbol P0.18 P0.19 P3.4 P3.5 P2.18 P2.19 P0.20 P0.21 P0.22 VSS(IO) P0.23 P2.20 TDI LQFP144 pin assignment ...continued Pin 132 133 134 135 136 137 138 139 140 141 142 143 144 Description Function 0 (default) GPIO 0, pin 18 GPIO 0, pin 19 GPIO 3, pin 4 GPIO 3, pin 5 GPIO 2, pin 18 GPIO 2, pin 19 GPIO 0, pin 20 GPIO 0, pin 21 GPIO 0, pin 22 ground for I/O GPIO 0, pin 23 GPIO 2, pin 20 ADC2 IN7 PWM2 MAT5 PWM2 CAP0 Function 1 ADC2 IN2 ADC2 IN3 TIMER3 MAT2 TIMER3 MAT3 ADC2 IN4 ADC2 IN5 ADC2 IN6 Function 2 PWM2 MAT0 PWM2 MAT1 PWM2 MAT4 PWM2 MAT5 PWM1 CAP1 PWM1 CAP2 PWM2 MAT2 PWM2 MAT3 PWM2 MAT4 D R Function 3 EXTBUS A14 EXTBUS A15 CAN1 TxD CAN1 RxD EXTBUS D16 EXTBUS D17 EXTBUS A16 EXTBUS A17 EXTBUS A18 EXTBUS A19 EXTBUS D18 R A FT D R R A F D R A FT A FT A FT D R A D FT D R A IEEE 1149.1 data in, pulled up internally. 7. Functional description 7.1 Reset, debug, test and power description 7.1.1 Reset and power-up behavior The LPC2917/19 contains external reset input and internal power-up reset circuits. This ensures that a reset is extended internally until the oscillators and flash have reached a stable state. See Section 11 for trip levels of the internal power-up reset circuit1. See Section 12 for characteristics of the several start-up and initialization times. Table 4 shows the reset pin. Table 4. Symbol RSTN Reset pin Direction in Description external reset input, active LOW; pulled up internally At activation of the RSTN pin the JTAGSEL pin is sensed as logic LOW. If this is the case the LPC2917/19 is assumed to be connected to debug hardware, and internal circuits re-program the source for the BASE_SYS_CLK to be the crystal oscillator instead of the Low-Power Ring Oscillator (LP_OSC). This is required because the clock rate when running at LP_OSC speed is too low for the external debugging environment. 7.1.2 Reset strategy The LPC2917/19 contains a central module, the Reset Generator Unit (RGU) in the Power, Clock and Reset Control Subsystem (PCRSS), which controls all internal reset signals towards the peripheral modules. The RGU provides individual reset control as well as the monitoring functions needed for tracing a reset back to source. 1. Only for 1.8 V power sources (c) NXP B.V. 2007. All rights reserved. LPC2917_19_1 Preliminary data sheet Rev. 1.01 -- 15 November 2007 10 of 68 D R A FT NXP Semiconductors LPC2917/19 FT FT FT D D R R A A A FT FT FT D D R A FT D R R A FT D D D R A D R ARM9 microcontroller with CAN and LIN A D R A D R A D D R A FT A FT D R FT R 7.1.3 IEEE 1149.1 interface pins (JTAG boundary-scan test) D R The LPC2917/19 contains boundary-scan test logic according to IEEE 1149.1, also referred to in this document as Joint Test Action Group (JTAG). The boundary-scan test pins can be used to connect a debugger probe for the embedded ARM processor. Pin JTAGSEL selects between boundary-scan mode and debug mode. Table 5 shows the boundary- scan test pins. D R A FT Table 5. Symbol JTAGSEL TRSTN TMS TDI TDO TCK IEEE 1149.1 boundary-scan test and debug interface Description TAP controller select input. LOW level selects ARM debug mode and HIGH level selects boundary scan and flash programming; pulled up internally test reset input; pulled up internally (active LOW) test-mode select input; pulled up internally test data input, pulled up internally test data output test clock input R A FT R A F D R A FT D R A FT D R A A FT D 7.1.4 Power supply pins description Table 6 shows the power supply pins. Table 6. Symbol VDD(CORE) VSS(CORE) VDD(IO) VSS(IO) VDD(OSC) VSS(OSC) VDD(A3V3) VSS(PLL) Power supplies Description digital core supply 1.8 V digital core ground (digital core, ADC 1) I/O pins supply 3.3 V I/O pins ground oscillator and PLL supply oscillator ground ADC 3.3 V supply PLL ground 7.2 Clocking strategy 7.2.1 Clock architecture The LPC2917/19 contains several different internal clock areas. Peripherals like Timers, SPI, UART, CAN and LIN have their own individual clock sources called Base Clocks. All base clocks are generated by the Clock Generator Unit (CGU). They may be unrelated in frequency and phase and can have different clock sources within the CGU. The system clock for the CPU and AHB Multilayer Bus infrastructure has its own base clock. This means most peripherals are clocked independently from the system clock. See Figure 3 for an overview of the clock areas within the device. Within each clock area there may be multiple branch clocks, which offers very flexible control for power-management purposes. All branch clocks are outputs of the Power Management Unit (PMU) and can be controlled independently. Branch clocks derived from the same base clock are synchronous in frequency and phase. See Section 8.8 for more details of clock and power control within the device. LPC2917_19_1 (c) NXP B.V. 2007. All rights reserved. Preliminary data sheet Rev. 1.01 -- 15 November 2007 11 of 68 D R A FT NXP Semiconductors LPC2917/19 FT FT FT D D R R A A A FT FT FT D D R A FT D R D R R A FT D D R A D R ARM9 microcontroller with CAN and LIN A D R A A FT D R A D R A FT D R A FT D D R A FT A FT D R FT D R A F R A FT D D R LPC2917/19 ITCM 16 Kb ARM968E-S DTCM 16 Kb R A FT D R A s SYS_CLK Vectored Interrupt Controller (VIC) AH B2D TL Bridge m IEEE 1149.1 JTAG TEST and DEBUG INTERFACE s s Embedded FLASH Memory 512 - 768 Kb s FLASH Memory Controller (FMC) s External Static Memory Controller (SMC) Embedded SRAM Memory 16 Kb SRAM Controller #1 Modulation and Sampling Control Subsystem MSCSS_CLK Timer 0, 1 (MTMR) AH B2VPB Bridge Embedded SRAM Memory 32 Kb s s SRAM Controller #0 PWM 0, 1, 2, 3 ADC_CLK ADC 1, 2 General Subsystem Chip Feature ID (CFID) s AHB2V PB Bridge System Control Unit (SCU) Event Router (ER) CAN Controller 0, 1 AH B2VPB Bridge IVNSS_CLK GLOBAL ACCEPTANCE FILTER 2 Kbyte Static RAM s Peripheral Subsystem General Purpose IO (GPIO) 0, 1, 2, 3 Timer (TMR) 0, 1, 2, 3 SPI 0, 1, 2 UART 0, 1 Watchdog Timer (WDT) TMR_CLK SPI_CLK UART_CLK SAFE_CLK LIN MASTER 0/1 s AHB 2VPB Bridge Power Clock Reset Control Subsystem Clock Generation Unit (CGU) s AH B2D TL Bridge PCR_CLK Reset Generation Unit (RGU) Power Management Unit (PMU) Fig 3. LPC2917/19 block diagram, overview of clock areas LPC2917_19_1 (c) NXP B.V. 2007. All rights reserved. Preliminary data sheet Rev. 1.01 -- 15 November 2007 12 of 68 D R A FT NXP Semiconductors LPC2917/19 FT FT FT D D R R A A A FT FT FT D D R A FT D R R A FT D D D R A D R ARM9 microcontroller with CAN and LIN A D R A D R A D D R A FT A FT D R FT R 7.2.2 Base clock and branch clock relationship D R The next table contains an overview of all the base blocks in the LPC2917/19 and their derived branch clocks. A short description is given of the hardware parts that are clocked with the individual branch clocks. In relevant cases more detailed information can be found in the specific subsystem description. Some branch clocks have special protection since they clock vital system parts of the device and should (for example) not be switched off. See Section 8.8.6 for more details of how to control the individual branch clocks. D R A FT D Table 7. Base clock and branch clock overview Branch clock name CLK_SAFE CLK_SYS_CPU CLK_SYS_SYS CLK_SYS_PCRSS CLK_SYS_FMC CLK_SYS_RAM0 CLK_SYS_RAM1 CLK_SYS_SMC CLK_SYS_GESS CLK_SYS_VIC CLK_SYS_PESS CLK_SYS_GPIO0 CLK_SYS_GPIO1 CLK_SYS_GPIO2 CLK_SYS_GPIO3 CLK_SYS_IVNSS_A BASE_PCR_CLK BASE_IVNSS_CLK CLK_PCR_SLOW CLK_IVNSS_VPB CLK_IVNSS_CANCA CLK_IVNSS_CANC0 CLK_IVNSS_CANC1 CLK_IVNSS_LIN0 CLK_IVNSS_LIN1 Parts of the device clocked by this branch clock Watchdog Timer ARM968E-S and TCMs AHB Bus infrastructure AHB side of bridge in PCRSS Flash-Memory Controller Embedded SRAM Controller 0 (32 KByte) Embedded SRAM Controller 1 (16 KByte) External Static-Memory Controller General Subsystem Vectored Interrupt Controller Peripheral Subsystem GPIO bank 0 GPIO bank 1 GPIO bank 2 GPIO bank 3 AHB side of bridge of IVNSS PCRSS, CGU, RGU and PMU logic clock VPB side of the IVNSS CAN controller Acceptance Filter CAN channel 0 CAN channel 1 LIN channel 0 LIN channel 1 [1], [3] [2] [4] R A FT R A F D R A FT D FT D R A R A A FT Base clock BASE_SAFE_CLK BASE_SYS_CLK Remark [1] LPC2917_19_1 (c) NXP B.V. 2007. All rights reserved. Preliminary data sheet Rev. 1.01 -- 15 November 2007 13 of 68 D R A FT NXP Semiconductors LPC2917/19 FT FT FT D D R R A A A FT FT FT D D R A FT D R R A FT D D D R A D R ARM9 microcontroller with CAN and LIN A D R A D R A D D R A FT A FT D R FT R Table 7. Base clock and branch clock overview ...continued Branch clock name CLK_MSCSS_VPB CLK_MSCSS_MTMR0 CLK_MSCSS_MTMR1 CLK_MSCSS_PWM0 CLK_MSCSS_PWM1 CLK_MSCSS_PWM2 CLK_MSCSS_PWM3 D R R A R A A Base clock BASE_MSCSS_CLK Parts of the device clocked by this branch clock VPB side of the MSCSS Timer 0 in the MSCSS Timer 1 in the MSCSS PWM 0 PWM 0 PWM 0 PWM 0 Remark FT D R A R A FT F FT D R A FT D FT D D R A CLK_MSCSS_ADC1_V VPB side of ADC 1 PB CLK_MSCSS_ADC2_V VPB side of ADC 2 PB BASE_UART_CLK BASE_SPI_CLK CLK_UART0 CLK_UART1 CLK_SPI0 CLK_SPI1 CLK_SPI2 BASE_TMR_CLK CLK_TMR0 CLK_TMR1 CLK_TMR2 CLK_TMR3 BASE_ADC_CLK CLK_ADC1 CLK_ADC2 BASE_CLK_TESTSHELL [1] [2] [3] [4] UART 0 interface clock UART 1 interface clock SPI 0 interface clock SPI 1 interface clock SPI 2 interface clock Timer 0 clock for counter part Timer 1 clock for counter part Timer 2 clock for counter part Timer 3 clock for counter part Control of ADC 1, capture sample result Control of ADC 2, capture sample result CLK_TESTSHELL_IP This clock is always on (cannot be switched off for system safety reasons) In the peripheral subsystem parts of the Timers, Watchdog Timer, SPI and UART have their own clock source. See Section 8.4 for details. In the Power Clock and Reset Control subsystem parts of the CGU, RGU PMU have their own clock source. See Section 8.8 for details. The clock should remain activated when system wake-up on timer or UART is required. 8. Block description 8.1 Flash memory controller 8.1.1 Overview The Flash Memory Controller (FMC) interfaces to the embedded flash memory for two tasks: * Providing memory data transfer * Memory configuration via triggering, programming and erasing LPC2917_19_1 (c) NXP B.V. 2007. All rights reserved. Preliminary data sheet Rev. 1.01 -- 15 November 2007 14 of 68 D R A FT NXP Semiconductors LPC2917/19 FT FT FT D D R R A A A FT FT FT D D R A FT D R D R R A FT D D R A D R ARM9 microcontroller with CAN and LIN A The flash memory has a 128-bit wide data interface and the flash controller offers two 128-bit buffer lines to improve system performance. The flash has to be programmed initially via JTAG. In-system programming must be supported by the boot loader. In-application programming is possible. Flash memory contents can be protected by disabling JTAG access. Suspension of burning or erasing is not supported. A FT D R A D R A D R A D R A FT FT D R D R A FT A FT D R FT D R A F R A FT D A FT D R The key features are: D R A * * * * Programming by CPU via AHB Programming by external programmer via JTAG JTAG access protection Burn-finished and erase-finished interrupt 8.1.2 Description After reset flash initialization is started, which takes tinit time, see Section 12. During this initialization flash access is not possible and AHB transfers to flash are stalled, blocking the AHB bus. During flash initialization the index sector is read to identify the status of the JTAG access protection and sector security. If JTAG access protection is active the flash is not accessible via JTAG. ARM debug facilities are disabled to protect the flash-memory contents against unwanted reading out externally. If sector security is active only the concerned sections are read. Flash can be read synchronously or asynchronously to the system clock. In synchronous operation the flash goes into standby after returning the read data. Started reads cannot be stopped, and speculative reading and dual buffering are therefore not supported. With asynchronous reading, transfer of the address to the flash and of read data from the flash is done asynchronously, giving the fastest possible response time. Started reads can be stopped, so speculative reading and dual buffering are supported. Buffering is offered because the flash has a 128-bit wide data interface while the AHB interface has only 32 bits. With buffering a buffer line holds the complete 128-bit flash word, from which four words can be read. Without buffering every AHB data port read starts a flash read. A flash read is a slow process compared to the minimum AHB cycle time, so with buffering the average read time is reduced. This can improve system performance. With single buffering the most recently read flash word remains available until the next flash read. When an AHB data-port read transfer requires data from the same flash word as the previous read transfer, no new flash read is done and the read data is given without wait cycles. When an AHB data-port read transfer requires data from a different flash word to that involved in the previous read transfer, a new flash read is done and wait states are given until the new read data is available. With dual buffering a secondary buffer line is used, the output of the flash being considered as the primary buffer. On a primary buffer hit data can be copied to the secondary buffer line, which allows the flash to start a speculative read of the next flash word. LPC2917_19_1 (c) NXP B.V. 2007. All rights reserved. Preliminary data sheet Rev. 1.01 -- 15 November 2007 15 of 68 D R A FT NXP Semiconductors LPC2917/19 FT FT FT D D R R A A A FT FT FT D D R A FT D R R A FT D D D R A D R ARM9 microcontroller with CAN and LIN A D R A D R A D D R A FT A FT D R FT R Both buffer lines are invalidated after: D R R A FT R A F A FT * * * * Initialization Configuration-register access Data-latch reading Index-sector reading D D R A FT D R A FT D A FT D R A R The modes of operation are listed in Table 8. Table 8. Flash read modes for single (non-linear) reads; one flash-word read per word read default mode of operation; most recently read flash word is kept until another flash word is required one flash-word read per word read most recently read flash word is kept until another flash word is required on a buffer miss a flash read is done, followed by at most one speculative read; optimized for execution of code with small loops (less than eight words) from flash most recently used flash word is copied into second buffer line; next flash-word read is started; highest performance for linear reads Synchronous timing No buffer line Single buffer line Asynchronous timing No buffer line Single buffer line Dual buffer line, single speculative Dual buffer line, always speculative 8.1.3 Flash memory controller pin description The flash memory controller has no external pins. However, the flash can be programmed via the JTAG pins, see Section 7.1.3. 8.1.4 Flash memory controller clock description The flash memory controller is clocked by CLK_SYS_FMC, see Section 7.2.2. 8.1.5 Flash layout The ARM processor can program the flash for ISP (In-System Programming) and IAP (InApplication Programming). Note that the flash always has to be programmed by `flash words' of 128 bits (four 32-bit AHB bus words, hence 16 bytes). The flash memory is organized into eight `small' sectors of 8 kB each and up to 11 `large' sectors of 64 kB each. The number of large sectors depends on the device type. A sector must be erased before data can be written to it. The flash memory also has sector-wise protection. Writing occurs per page which consists of 4096 bits (32 flash words). A small sector contains 16 pages; a large sector contains 128 pages. Table 9 gives an overview of the flash-sector base addresses. Table 9. 0 1 2 LPC2917_19_1 Flash sector overview Sector size (kB) 8 8 8 Sector base address 0000 0000h 0000 2000h 0000 4000h (c) NXP B.V. 2007. All rights reserved. Sector number Preliminary data sheet Rev. 1.01 -- 15 November 2007 16 of 68 D R A FT NXP Semiconductors LPC2917/19 FT FT FT D D R R A A A FT FT FT D D R A FT D R R A FT D D D R A D R ARM9 microcontroller with CAN and LIN A D R A D R A D D R A FT A FT D R FT R Table 9. 3 4 5 6 7 8 9 10 11 12 13 14 15[1] 16[1] 17[1] 18[1] [1] Flash sector overview ...continued Sector size (kB) 8 8 8 8 8 64 64 64 64 64 64 64 64 64 64 64 Sector base address 0000 6000h 0000 8000h 0000 A000h 0000 C000h 0000 E000h 0001 0000h 0002 0000h 0003 0000h 0004 0000h 0005 0000h 0006 0000h 0007 0000h 0008 0000h 0009 0000h 000A 0000h 000B 0000h D R R A R A A Sector number FT D R R A FT D R A FT A F Availability of sector 15 to sector 18 depends on device type, see Section 4 "Ordering information". The index sector is a special sector in which the JTAG access protection and sector security are located. The address space becomes visible by setting the FS_ISS bit and overlaps the regular flash sector's address space. Note that the index sector cannot be erased, and that access to it has to be performed via code outside the flash. FT D FT D D R A 8.1.6 Flash bridge wait-states To eliminate the delay associated with synchronizing flash-read data, a predefined number of wait-states must be programmed. These depend on flash-memory response time and system clock period. The minimum wait-states value can be calculated with the following formulas: Synchronous reading: t acc ( clk ) WST > ----------------- - 1 tt tclk ( sys ) Asynchronous reading: t acc ( addr ) WST > --------------------- - 1 t tclk ( sys ) LPC2917_19_1 (c) NXP B.V. 2007. All rights reserved. Preliminary data sheet Rev. 1.01 -- 15 November 2007 17 of 68 D R A FT NXP Semiconductors LPC2917/19 FT FT FT D D R R A A A FT FT FT D D R A FT D R D R R A FT D D R A D R ARM9 microcontroller with CAN and LIN A Remark: If the programmed number of wait-states is more than three, flash-data reading cannot be performed at full speed (i.e. with zero wait-states at the AHB bus) if speculative reading is active. R A A FT D R A FT D R A D R A D FT D R A FT A FT D R FT D R A F R A FT D D R 8.2 External static memory controller 8.2.1 Overview The LPC2917/19 contains an external Static Memory Controller (SMC) which provides an interface for external (off-chip) memory devices. Key features are: * Supports static memory-mapped devices including RAM, ROM, flash, burst ROM and external I/O devices D R A FT D R A * * * * * * * * * * Asynchronous page-mode read operation in non-clocked memory subsystems Asynchronous burst-mode read access to burst-mode ROM devices Independent configuration for up to eight banks, each up to 16 MB Programmable bus-turnaround (idle) cycles (one to 16) Programmable read and write wait states (up to 32), for static RAM devices Programmable initial and subsequent burst-read wait state for burst-ROM devices Programmable write protection Programmable burst-mode operation Programmable external data width: 8-bit, 16-bit or 32-bit Programmable read-byte lane enable control 8.2.2 Description The SMC simultaneously supports up to eight independently configurable memory banks. Each memory bank can be 8, 16 or 32 bits wide and is capable of supporting SRAM, ROM, burst-ROM memory or external I/O devices. A separate chip-select output is available for each bank. The chip-select lines are configurable to be active HIGH or LOW. Memory-bank selection is controlled by memory addressing. Table 10 shows how the 32-bit system address is mapped to the external bus memory base addresses, chip selects and bank internal addresses. Table 10. External memory-bank address bit description Symbol Description 32 bit System Address Bit field 31 to 29 BA[2:0] external static-memory base address (three most significant bits); the base address can be found in the memory map; see Ref. 1. This field contains '010' when addressing an external memory bank. chip-select address space for eight memory banks; see [1] always '00'; other values are 'mirrors' of the 16 MByte bank address 16-MByte memory banks address space 28 to 26 25 and 24 23 to 0 CS[2:0] A[23:0] LPC2917_19_1 (c) NXP B.V. 2007. All rights reserved. Preliminary data sheet Rev. 1.01 -- 15 November 2007 18 of 68 D R A FT NXP Semiconductors LPC2917/19 FT FT FT D D R R A A A FT FT FT D D R A FT D D R R A FT D D R A D R ARM9 microcontroller with CAN and LIN A D R A D R A D D R A FT A FT D R FT D R Table 11. CS[2:0] 000 001 010 011 100 101 110 111 External static-memory controller banks Bank bank 0 bank 1 bank 2 bank 3 bank 4 bank 5 bank 6 bank 7 R R A FT D R R A F D R A FT A FT A FT D R A D FT D R A 8.2.3 External static-memory controller pin description The external static-memory controller module in the LPC2917/19 has the following pins, which are combined with other functions on the port pins of the LPC2917/19. Table 12 shows the external memory controller pins. Table 12. Symbol EXTBUS CSx EXTBUS BLSy EXTBUS WE_N EXTBUS OE_N External memory controller pins Direction out out out out Description memory-bank x select, x runs from 0 to 7 byte-lane select input y, y runs from 0 to 3 write enable (active LOW) output enable (active LOW) address bus data bus EXTBUS A[23:0] out EXTBUS D[31:0] in/out 8.2.4 External static-memory controller clock description The External Static-Memory Controller is clocked by CLK_SYS_SMC, see Section 7.2.2. 8.2.5 External memory timing diagrams A timing diagram for reading from external memory is shown in Figure 4. The relationship between the wait-state settings is indicated with arrows. LPC2917_19_1 (c) NXP B.V. 2007. All rights reserved. Preliminary data sheet Rev. 1.01 -- 15 November 2007 19 of 68 D R A FT NXP Semiconductors LPC2917/19 FT FT FT D D R R A A A FT FT FT D D R A FT D R D R R A FT D D R A D R ARM9 microcontroller with CAN and LIN A D R A A FT D R A D R A FT D R A FT D R A FT A FT D R FT D R A F R A FT D R CLK(SYS) D D R A FT D CS R A OE_N ADDR DATA WSTOEN WST1 WSTOEN=3, WST1=7 Fig 4. Reading from external memory A timing diagram for writing to external memory is shown In Figure 5. The relationship between wait-state settings is indicated with arrows. CLK(SYS) CS WE_N / BLS ADDR DATA WSTWEN WST2 WSTWEN=3, WST2=7 Fig 5. Writing to external memory LPC2917_19_1 (c) NXP B.V. 2007. All rights reserved. Preliminary data sheet Rev. 1.01 -- 15 November 2007 20 of 68 D R A FT NXP Semiconductors LPC2917/19 FT FT FT D D R R A A A FT FT FT D D R A FT D R D R R A FT D D R A D R ARM9 microcontroller with CAN and LIN A Usage of the idle/turn-around time (IDCY) is demonstrated In Figure 6. Extra wait states are added between a read and a write cycle in the same external memory device. R A A FT D R A FT D R A D R A D FT D R D R A FT A FT D R FT D R A F R A FT D A FT D R CLK(SYS) D R A CS WE_N / BLS OE_N ADDR DATA WSTOEN WST1 IDCY WSTWEN WST2 WSTOEN=5, WSTWEN=5, WST1=7, WST2=6, IDCY=5 Fig 6. Reading/writing external memory Address pins on the device are shared with other functions. When connecting external memories, check that the I/O pin is programmed for the correct function. Control of these settings is handled by the SCU. LPC2917_19_1 (c) NXP B.V. 2007. All rights reserved. Preliminary data sheet Rev. 1.01 -- 15 November 2007 21 of 68 D R A FT NXP Semiconductors LPC2917/19 FT FT FT D D R R A A A FT FT FT D D R A FT D R R A FT D D D R A D R ARM9 microcontroller with CAN and LIN A D R A D R A D D R A FT A FT D R FT R 8.3 General subsystem 8.3.1 General subsystem clock description D R R A FT D R R A F D R A FT A FT A FT The general subsystem is clocked by CLK_SYS_GESS, see Section 7.2.2. D D R A 8.3.2 Chip and feature identification 8.3.2.1 Overview The key features are: FT D R A * Identification of product * Identification of features enabled 8.3.2.2 Description The Chip/Feature ID (CFID) module contains registers which show and control the functionality of the chip. It contains an ID to identify the silicon, and also registers containing information about the features enabled or disabled on the chip. 8.3.2.3 CFID pin description The CFID has no external pins. 8.3.3 System Control Unit (SCU) 8.3.3.1 Overview The system control unit takes care of system-related functions.The key feature is configuration of the I/O port-pins multiplexer. 8.3.3.2 Description The system control unit defines the function of each I/O pin of the LPC2917/19. The I/O pin configuration should be consistent with peripheral function usage. 8.3.3.3 SCU pin description The SCU has no external pins. 8.3.4 Event router 8.3.4.1 Overview The event router provides bus-controlled routing of input events to the vectored interrupt controller for use as interrupt or wake-up signals. Key features: * Up to 24 level-sensitive external interrupt pins, including CAN, LIN and RxD wake-up features plus three internal event sources * * * * * LPC2917_19_1 Input events can be used as interrupt source either directly or latched (edge-detected) Direct events disappear when the event becomes inactive Latched events remain active until they are explicitly cleared Programmable input level and edge polarity Event detection maskable (c) NXP B.V. 2007. All rights reserved. Preliminary data sheet Rev. 1.01 -- 15 November 2007 22 of 68 D R A FT NXP Semiconductors LPC2917/19 FT FT FT D D R R A A A FT FT FT D D R A FT D R R A FT D D D R A D R ARM9 microcontroller with CAN and LIN A D R A D R A D D R A FT A FT D R FT R * Event detection is fully asynchronous, so no clock is required 8.3.4.2 Description D R The event router allows the event source to be defined, its polarity and activation type to be selected and the interrupt to be masked or enabled. The event router can be used to start a clock on an external event. FT R A FT D R R A F D R A FT D A FT A D R A FT D R The vectored interrupt-controller inputs are active HIGH. 8.3.4.3 Event-router pin description and mapping to register bit positions The event router module in the LPC2917/19 is connected to the pins listed below. The pins are combined with other functions on the port pins of the LPC2917/19. Table 13 shows the pins connected to the event router, and also the corresponding bit position in the event-router registers and the default polarity. Table 13. Symbol EXTINT0 EXTINT1 EXTINT2 EXTINT3 EXTINT4 EXTINT5 EXTINT6 EXTINT7 CAN0 RXD CAN1 RXD LIN0 RXD LIN1 RXD Event-router pin connections Direction in in in in in in in in in in in in na na na Bit position 0 1 2 3 4 5 6 7 8 9 13 - 10 14 15 21 - 16 22 23 24 26 - 25 Description external interrupt input 0 external interrupt input 1 external interrupt input 2 external interrupt input 3 external interrupt input 4 external interrupt input 5 external interrupt input 6 external interrupt input 7 CAN0 receive data input wake-up CAN1 receive data input wake-up reserved LIN0 receive data input wake-up LIN1 receive data input wake-up reserved CAN interrupt (internal) VIC FIQ (internal) VIC IRQ (internal) reserved Default polarity 1 1 1 1 1 1 1 1 0 0 0 0 1 1 1 - A 8.4 Peripheral subsystem 8.4.1 Peripheral subsystem clock description The peripheral subsystem is clocked by a number of different clocks: * * * * LPC2917_19_1 CLK_SYS_PESS CLK_UART0/1 CLK_SPI0/1/2 CLK_TMR0/1/2/3 (c) NXP B.V. 2007. All rights reserved. Preliminary data sheet Rev. 1.01 -- 15 November 2007 23 of 68 D R A FT NXP Semiconductors LPC2917/19 FT FT FT D D R R A A A FT FT FT D D R A FT D R R A FT D D D R A D R ARM9 microcontroller with CAN and LIN A D R A D R A D D R A FT A FT D R FT R * CLK_SAFE see Section 7.2.2 8.4.2 Watchdog timer 8.4.2.1 Overview D R The purpose of the watchdog timer is to reset the ARM9 processor within a reasonable amount of time if the processor enters an error state. The watchdog generates a system reset if the user program fails to trigger it correctly within a predetermined amount of time. Key features: R A FT D R R A F D R A FT A FT A FT D R A D FT D R A * * * * * * 8.4.2.2 Internal chip reset if not periodically triggered Timer counter register runs on always-on safe clock Optional interrupt generation on watchdog timeout Debug mode with disabling of reset Watchdog control register change-protected with key Programmable 32-bit watchdog timer period with programmable 32-bit prescaler. Description The watchdog timer consists of a 32-bit counter with a 32-bit prescaler. The watchdog should be programmed with a time-out value and then periodically restarted. When the watchdog times out it generates a reset through the RGU. To generate watchdog interrupts in watchdog debug mode the interrupt has to be enabled via the interrupt enable register. A watchdog-overflow interrupt can be cleared by writing to the clear-interrupt register. Another way to prevent resets during debug mode is via the Pause feature of the Watchdog Timer. The watchdog is stalled when the ARM9 is in debug mode and the PAUSE_ENABLE bit in the Watchdog Timer Control register is set. The Watchdog Reset output is fed to the Reset Generator Unit (RGU). The RGU contains a reset source register to identify the reset source when the device has gone through a reset. See Section 8.8.5. 8.4.2.3 Pin description The watchdog has no external pins. 8.4.2.4 Watchdog timer clock description The Watchdog Timer is clocked by two different clocks; CLK_SYS_PESS and CLK_SAFE, see Section 7.2.2. The register interface towards the system bus is clocked by CLK_SYS_PESS. The timer and prescale counters are clocked by CLK_SAFE which is always on. 8.4.3 Timer 8.4.3.1 Overview The LPC2917/19 contains six identical timers: four in the peripheral subsystem and two in the Modulation and Sampling Control SubSystem (MSCSS) located at different peripheral base addresses. This section describes the four timers in the peripheral subsystem. Each LPC2917_19_1 (c) NXP B.V. 2007. All rights reserved. Preliminary data sheet Rev. 1.01 -- 15 November 2007 24 of 68 D R A FT NXP Semiconductors LPC2917/19 FT FT FT D D R R A A A FT FT FT D D R A FT D R D R R A FT D D R A D R ARM9 microcontroller with CAN and LIN A timer has four capture inputs and/or match outputs. Connection to device pins depends on the configuration programmed into the port function-select registers. The two timers located in the MSCSS have no external capture or match pins, but the memory map is identical, see Section 8.7.7. One of these timers has an external input for a pause function. R A A FT D R A FT D D R A D R A D FT R D R A FT A FT D R FT D R A F R A FT D FT D A R The key features are: D R A * 32-bit timer/counter with programmable 32-bit prescaler * Up to four 32-bit capture channels per timer. These take a snapshot of the timer value when an external signal connected to the TIMERx CAPn input changes state. A capture event may also optionally generate an interrupt * Four 32-bit match registers per timer that allow: - Continuous operation with optional interrupt generation on match - Stop timer on match with optional interrupt generation - Reset timer on match with optional interrupt generation * Up to four external outputs per timer corresponding to match registers, with the following capabilities: - Set LOW on match - Set HIGH on match - Toggle on match - Do nothing on match * Pause input pin (MSCSS timers only) 8.4.3.2 Description The timers are designed to count cycles of the clock and optionally generate interrupts or perform other actions at specified timer values, based on four match registers. They also include capture inputs to trap the timer value when an input signal changes state, optionally generating an interrupt. The core function of the timers consists of a 32 bit `prescale counter' triggering the 32 bit `timer counter'. Both counters run on clock CLK_TMRx (x runs from 0 to 3) and all time references are related to the period of this clock. Note that each timer has its individual clock source within the Peripheral SubSystem. In the Modulation and Sampling SubSystem each timer also has its own individual clock source. See section Section 8.8.6 for information on generation of these clocks. 8.4.3.3 Pin description The four timers in the peripheral subsystem of the LPC2917/19 have the pins described below. The two timers in the modulation and sampling subsystem have no external pins except for the pause pin on MSCSS timer 1. See Section 8.7.7 for a description of these timers and their associated pins. The timer pins are combined with other functions on the port pins of the LPC2917/19, see Section 8.3.3. Table Table 14 shows the timer pins (x runs from 0 to 3). LPC2917_19_1 (c) NXP B.V. 2007. All rights reserved. Preliminary data sheet Rev. 1.01 -- 15 November 2007 25 of 68 D R A FT NXP Semiconductors LPC2917/19 FT FT FT D D R R A A A FT FT FT D D R A FT D D R R A FT D D R A D R ARM9 microcontroller with CAN and LIN A D R A D R A D D R A FT A FT D R FT D R Table 14. Symbol Timer pins Direction IN IN IN IN OUT OUT OUT OUT Description TIMER x capture input 0 TIMER x capture input 1 TIMER x capture input 2 TIMER x capture input 3 TIMER x match output 0 TIMER x match output 1 TIMER x match output 2 TIMER x match output 3 R R A FT D R R A F D R A FT TIMERx CAP[0] TIMERx CAP[1] TIMERx CAP[2] TIMERx CAP[3] TIMERx MAT[0] TIMERx MAT[1] TIMERx MAT[2] TIMERx MAT[3] A A FT D R A FT D FT D R A 8.4.3.4 Timer clock description The timer modules are clocked by two different clocks; CLK_SYS_PESS and CLK_TMRx (x = 0-3), see Section 7.2.2. Note that each timer has its own CLK_TMRx branch clock for power management. The frequency of all these clocks is identical as they are derived from the same base clock BASE_CLK_TMR. The register interface towards the system bus is clocked by CLK_SYS_PESS. The timer and prescale counters are clocked by CLK_TMRx. 8.4.4 UARTs 8.4.4.1 Overview The LPC2917/19 contains two identical UARTs located at different peripheral base addresses. The key features are: * * * * 8.4.4.2 16-byte receive and transmit FIFOs Registers conform to industry standard 550 Receiver FIFO trigger points at 1 byte, 4 bytes, 8 bytes and 14 bytes Built-in baud-rate generator Description The UART is commonly used to implement a serial interface such as RS232. The LPC2917/19 contains two industry-standard 550 UARTs with 16-byte transmit and receive FIFOs, but they can also be put into 450 mode without FIFOs. 8.4.4.3 UART pin description The two UARTs in the LPC2917/19 have the following pins. The UART pins are combined with other functions on the port pins of the LPC2917/19. Table 15 shows the UART pins (x runs from 0 to 1). Table 15. Symbol UARTx TXD UARTx RXD UART pins Direction out in Description UART channel x transmit data output UART channel x receive data input LPC2917_19_1 (c) NXP B.V. 2007. All rights reserved. Preliminary data sheet Rev. 1.01 -- 15 November 2007 26 of 68 D R A FT NXP Semiconductors LPC2917/19 FT FT FT D D R R A A A FT FT FT D D R A FT D R R A FT D D D R A D R ARM9 microcontroller with CAN and LIN A D R A D R A D D R A FT A FT D R FT R 8.4.4.4 UART clock description D R The UART modules are clocked by two different clocks; CLK_SYS_PESS and CLK_UARTx (x = 0-1), see Section 7.2.2. Note that each UART has its own CLK_UARTx branch clock for power management. The frequency of all CLK_UARTx clocks is identical since they are derived from the same base clock BASE_CLK_UART. The register interface towards the system bus is clocked by CLK_SYS_PESS. The baud generator is clocked by the CLK_UARTx. D R A FT D R A FT R A F D R A FT D FT D R A R A A FT 8.4.5 Serial peripheral interface 8.4.5.1 Overview The LPC2917/19 contains three Serial Peripheral Interface modules (SPIs) to allow synchronous serial communication with slave or master peripherals. The key features are: * * * * Master or slave operation Supports up to four slaves in sequential multi-slave operation Supports timer-triggered operation Programmable clock bit rate and prescale based on SPI source clock (BASE_SPI_CLK), independent of system clock * Separate transmit and receive FIFO memory buffers; 16 bits wide, 32 locations deep * Programmable choice of interface operation: Motorola SPI or Texas Instruments Synchronous Serial Interfaces * * * * * 8.4.5.2 Programmable data-frame size from 4 to 16 bits Independent masking of transmit FIFO, receive FIFO and receive overrun interrupts Serial clock-rate master mode: fserial_clk fCLK(SPI)*/2 Serial clock-rate slave mode: fserial_clk = fCLK(SPI)*/4 Internal loopback test mode Functional description The SPI module is a master or slave interface for synchronous serial communication with peripheral devices that have either Motorola SPI or Texas Instruments Synchronous Serial Interfaces. The SPI module performs serial-to-parallel conversion on data received from a peripheral device. The transmit and receive paths are buffered with FIFO memories (16 bits wide x 32 words deep). Serial data is transmitted on SPI_TxD and received on SPI_RxD. The SPI module includes a programmable bit-rate clock divider and prescaler to generate the SPI serial clock from the input clock CLK_SPIx. The SPI module's operating mode, frame format, and word size are programmed through the SLVn_SETTINGS registers. A single combined interrupt request SPI_INTREQ output is asserted if any of the interrupts are asserted and unmasked. LPC2917_19_1 (c) NXP B.V. 2007. All rights reserved. Preliminary data sheet Rev. 1.01 -- 15 November 2007 27 of 68 D R A FT NXP Semiconductors LPC2917/19 FT FT FT D D R R A A A FT FT FT D D R A FT D R D R R A FT D D R A D R ARM9 microcontroller with CAN and LIN A Depending on the operating mode selected, the SPI_CS_OUT outputs operate as an active-HIGH frame synchronization output for Texas Instruments synchronous serial frame format or an active-LOW chip select for SPI. Each data frame is between four and 16 bits long, depending on the size of words programmed, and is transmitted starting with the MSB. There are two basic frame types that can be selected: A FT D R A D R A D R A D R A FT FT D R D R A FT A FT D R FT D R A F R A FT D A FT D R A D R * Texas Instruments synchronous serial * Motorola Serial Peripheral Interface 8.4.5.3 Modes of operation The SPI module can operate in: * Master mode: - Normal transmission mode - Sequential slave mode * Slave mode 8.4.5.4 SPI pin description The three SPI modules in the LPC2917/19 have the pins listed below. The pins are combined with other functions on the port pins of the LPC2917/19, see Section 8.3.3. Table 16 shows the SPI pins (x runs from 0 to 2; y runs from 0 to 3). Table 16. Symbol SPIx SCSy SPIx SCK SPIx SDI SPIx SDO [1] [2] SPI pins Direction in/out in/out in out Description SPIx chip select[1][2] SPIx clock[1] SPIx data input SPIx data output Direction of SPIx SCS and SPIx SCK pins depends on master or slave mode. These pins are output in master mode, input in slave mode. In slave mode there is only one chip-select input pin, SPIx SCS0. The other chip selects have no function in slave mode. 8.4.5.5 SPI clock description The SPI modules are clocked by two different clocks; CLK_SYS_PESS and CLK_SPIx (x = 0-2), see Section 7.2.2. Note that each SPI has its own CLK_SPIx branch clock for power management. The frequency of all clocks CLK_SPIx is identical as they are derived from the same base clock BASE_CLK_SPI. The register interface towards the system bus is clocked by CLK_SYS_PESS. The serial-clock rate divisor is clocked by CLK_SPIx. The SPI clock frequency can be controlled by the CGU. In master mode the SPI clock frequency (CLK_SPIx) must be set to at least twice the SPI serial clock rate on the interface. In slave mode CLK_SPIx must be set to four times the SPI serial clock rate on the interface. LPC2917_19_1 (c) NXP B.V. 2007. All rights reserved. Preliminary data sheet Rev. 1.01 -- 15 November 2007 28 of 68 D R A FT NXP Semiconductors LPC2917/19 FT FT FT D D R R A A A FT FT FT D D R A FT D R R A FT D D D R A D R ARM9 microcontroller with CAN and LIN A D R A D R A D D R A FT A FT D R FT R 8.4.6 General-purpose I/O 8.4.6.1 Overview D R The LPC2917/19 contains four general-purpose I/O ports located at different peripheral base addresses. In the 144-pin package all four ports are available. All I/O pins are bi-directional, and the direction can be programmed individually. The I/O pad behavior depends on the configuration programmed in the port function-select registers. FT R A FT D R R A F D R A FT D A FT A D R A FT D R A The key features are: * * * * 8.4.6.2 General-purpose parallel inputs and outputs Direction control of individual bits Synchronized input sampling for stable input-data values All I/O defaults to input at reset to avoid any possible bus conflicts Description The general-purpose I/O provides individual control over each bi-directional port pin. There are two registers to control I/O direction and output level. The inputs are synchronized to achieve stable read-levels. To generate an open-drain output, set the bit in the output register to the desired value. Use the direction register to control the signal. When set to output, the output driver actively drives the value on the output: when set to input the signal floats and can be pulled up internally or externally. 8.4.6.3 GPIO pin description The five GPIO ports in the LPC2917/19 have the pins listed below. The GPIO pins are combined with other functions on the port pins of the LPC2917/19. Table 17 shows the GPIO pins. Table 17. Symbol GPIO0 pin[31:0] GPIO1 pin[31:0] GPIO2 pin[27:0] GPIO3 pin[15:0] GPIO pins Direction in/out in/out in/out in/out Description GPIO port x pins 31 to 0 GPIO port x pins 31 to 0 GPIO port x pins 27 to 0 GPIO port x pins 15 to 0 8.4.6.4 GPIO clock description The GPIO modules are clocked by several clocks, all of which are derived from BASE_SYS_CLK; CLK_SYS_PESS and CLK_SYS_GPIOx (x = 0-3), see Section 7.2.2. Note that each GPIO has its own CLK__SYS_GPIOx branch clock for power management. The frequency of all clocks CLK_SYS_GPIOx is identical to CLK_SYS_PESS since they are derived from the same base clock BASE_SYS_CLK. LPC2917_19_1 (c) NXP B.V. 2007. All rights reserved. Preliminary data sheet Rev. 1.01 -- 15 November 2007 29 of 68 D R A FT NXP Semiconductors LPC2917/19 FT FT FT D D R R A A A FT FT FT D D R A FT D R R A FT D D D R A D R ARM9 microcontroller with CAN and LIN A D R A D R A D D R A FT A FT D R FT R 8.5 CAN gateway 8.5.1 Overview D R Controller Area Network (CAN) is the definition of a high-performance communication protocol for serial data communication. The two CAN controllers in the LPC2917/19 provide a full implementation of the CAN protocol according to the CAN specification version 2.0B. The gateway concept is fully scalable with the number of CAN controllers, and always operates together with a separate powerful and flexible hardware acceptance filter. D R A FT D R R A F D R A FT A FT A FT R A D FT D R A The key features are: * * * * * * * * Supports 11-bit as well as 29-bit identifiers Double receive buffer and triple transmit buffer Programmable error-warning limit and error counters with read/write access Arbitration-lost capture and error-code capture with detailed bit position Single-shot transmission (i.e. no re-transmission) Listen-only mode (no acknowledge; no active error flags) Reception of `own' messages (self-reception request) Full CAN mode for message reception 8.5.2 Global acceptance filter The global acceptance filter provides look-up of received identifiers - called acceptance filtering in CAN terminology - for all the CAN controllers. It includes a CAN ID look-up table memory, in which software maintains one to five sections of identifiers. The CAN ID look-up table memory is 2 kB large (512 words, each of 32 bits). It can contain up to 1024 standard frame identifiers (SFF) or 512 extended frame identifiers (EFF) or a mixture of both types. It is also possible to define identifier groups for standard and extended message formats. 8.5.3 CAN pin description The two CAN controllers in the LPC2917/19 have the pins listed below. The CAN pins are combined with other functions on the port pins of the LPC2917/19. Table 18 shows the CAN pins (x runs from 0 to 1). Table 18. Symbol CANx TXDC CAN pins Direction out Description CAN channel x transmit data output CAN channel x receive data input CANx RXDC in 8.6 LIN 8.6.1 Overview The LPC2917/19 contain two LIN 2.0 master controllers. These can be used as dedicated LIN 2.0 master controllers with additional support for sync break generation and with hardware implementation of the LIN protocol according to spec 2.0. The key features are: LPC2917_19_1 (c) NXP B.V. 2007. All rights reserved. Preliminary data sheet Rev. 1.01 -- 15 November 2007 30 of 68 D R A FT NXP Semiconductors LPC2917/19 FT FT FT D D R R A A A FT FT FT D D R A FT D R R A FT D D D R A D R ARM9 microcontroller with CAN and LIN A D R A D R A D D R A FT A FT D R FT R * * * * * * * * * * Complete LIN 2.0 message handling and transfer One interrupt per LIN message Slave response time-out detection Programmable sync-break length Automatic sync-field and sync-break generation Programmable inter-byte space Hardware or software parity generation Automatic checksum generation Fault confinement Fractional baud-rate generator D R R A FT D R R A F D R A FT A FT A FT D R A D FT D R A 8.6.2 LIN pin description The two LIN 2.0 master controllers in the LPC2917/19 have the pins listed below. The LIN pins are combined with other functions on the port pins of the LPC2917/19. Table 19 shows the LIN pins. For more information see Ref. 1 subsection 3.43, LIN master controller. Table 19. Symbol LIN controller pins Direction Description LIN channel 0/1 transmit data output LIN channel 0/1 receive data input LIN0/1 TXDL out LIN0/1 RXDL in 8.7 Modulation and sampling control subsystem 8.7.1 Overview The Modulation and Sampling Control Subsystem (MSCSS) in the LPC2917/19 includes four Pulse-Width Modulators (PWMs), three10-bit successive approximation Analog-to-Digital Converters (ADCs) and two timers. The key features of the MSCSS are: * Two 10-bit, 400 ksamples/s, 8-channel ADCs with 3.3 V inputs and various triggerstart options * Four 6-channel PWMs (Pulse-Width Modulators) with capture and trap functionality * Two dedicated timers to schedule and synchronize the PWMs and ADCs 8.7.2 Description The MSCSS contains Pulse-Width Modulators (PWMs), Analog-to-Digital Converters (ADCs) and timers. Figure 7 provides an overview of the MSCSS. An AHB-to-VPB bus bridge takes care of communication with the AHB system bus. Two internal timers are dedicated to this subsystem. MSCSS timer 0 can be used to generate start pulses for the ADCs and the first PWM. The second timer (MSCSS timer 1) is used to generate `carrier' signals for the PWMs. These carrier patterns can be used, for example, in applications requiring current LPC2917_19_1 (c) NXP B.V. 2007. All rights reserved. Preliminary data sheet Rev. 1.01 -- 15 November 2007 31 of 68 D R A FT NXP Semiconductors LPC2917/19 FT FT FT D D R R A A A FT FT FT D D R A FT D R D R R A FT D D R A D R ARM9 microcontroller with CAN and LIN A control. Several other trigger possibilities are provided for the ADCs (external, cascaded or following a PWM). The capture inputs of both timers can also be used to capture the start pulse of the ADCs. R A The PWMs can be used to generate waveforms in which the frequency, duty cycle and rising and falling edges can be controlled very precisely. Capture inputs are provided to measure event phases compared to the main counter. Depending on the applications, these inputs can be connected to digital sensor motor outputs or digital external signals. Interrupt signals are generated on several events to closely interact with the CPU. The ADCs can be used for any application needing accurate digitized data from analog sources. To support applications like motor control, a mechanism to synchronize several PWMs and ADCs is available (sync_in and sync_out). Note that the PWMs run on the PWM clock and the ADCs on the ADC clock, see Section 8.8.4. D R A A FT D R A D FT D R A FT D R D R A FT A FT D R FT D R A F R A FT D A FT D R A D R ADC2 IN[7:0] ADC2_EXT_START ADC1 IN[7:0] ADC1_EXT_START ADC clock MSCSS TIMER 0 ADC CONTROL AHB system bus VPB sub system bus (to all sub blocks) SYNCS ADC 1 3.3 V ADC 2 3.3 V MSCSS TIMER 1 PWM CONTROL CARRIERS PWM 0 PWM 1 PWM 2 PWM 3 PWM0 MAT[5:0] PWM1 MAT[5:0] PWM2 MAT[5:0] PWM3 MAT[5:0] AHB2VPB BRIDGE PWM0 TRAP PWM0 CAP[2:0] PWM1 TRAP PWM1 CAP[2:0] PWM2 TRAP PWM2 CAP[2:0] PWM3 TRAP PWM3 CAP[2:0] 002aad348 Fig 7. Modulation and sampling control subsystem block diagram 8.7.2.1 Synchronization and trigger features of the MSCSS The MSCSS contains two internal timers to generate synchronization and carrier pulses for the ADCs and PWMs. Figure 8 shows how the timers are connected to the ADC and PWM modules. LPC2917_19_1 (c) NXP B.V. 2007. All rights reserved. Preliminary data sheet Rev. 1.01 -- 15 November 2007 32 of 68 D R A FT NXP Semiconductors LPC2917/19 FT FT FT D D R R A A A FT FT FT D D R A FT D R D R R A FT D D R A D R ARM9 microcontroller with CAN and LIN A Each ADC module has four start inputs. An ADC conversion is started when one of the start ADC conditions is valid: R A FT D R A * start 0: ADC external start input pin; can be triggered at a positive or negative edge. FT D R A D R A D A FT D R A FT A FT D R FT D R A F R A FT D R Note that this signal is captured in the ADC clock domain D * start 1: If the `preceding' ADC conversion is ended, the sync_out signal starts an ADC conversion. This signal is captured in the MSCSS subsystem clock domain, see Section 8.7.5.2. As can be seen in Figure 8, the sync_out of ADC1 is connected to the start 1 input of ADC2 and the sync_out of ADC2 is connected to the start 1 input of ADC1. D R A FT D R A * start 2: The PWM sync_out can start an ADC conversion. The sync_out signal is synchronized to the ADC clock in the ADC module. This signal is captured in the MSCSS subsystem clock domain. * start 3: The match outputs from MSCSS timer 0 are connected to the start 3 inputs of the ADCs. This signal is captured in the ADC clock domain. The PWM_sync and trans_enable_in of PWM 0 are connected to the 4th match output of MSCSS timer 0 to start the PWM after a pre-programmed delay. This sync signal is cascaded through all PWMs, allowing a programmable delay offset between subsequent PWMs. The sync delay of each PWM can be programmed synchronously or with a different phase for spreading the power load. The match outputs of MSCSS timer 1 (PWM control) are connected to the corresponding carrier inputs of the PWM modules. The carrier signal is modulated with the PWMgenerated waveforms. The pause input of MSCSS timer 1 (PWM Control) is connected to an external input pin. Generation of the carrier signal is stopped by asserting the pause of this timer. The pause input of MSCSS timer 0 (ADC Control) is connected to a `NOR' of the PWM_sync outputs (start 2 input on the ADCs). If the pause feature of this timer is enabled the timer only counts when one of the PWM_sync outputs is active HIGH. This feature can be used to start the ADC once every x PWM cycles, where x corresponds to the value in the match register of the timer. In this case the start 3 input of the ADC should be enabled (start on match output of MSCSS timer 0). The signals connected to the capture inputs of the timers (both MSCSS timer 0 and MSCSS timer 1) are intended for debugging. LPC2917_19_1 (c) NXP B.V. 2007. All rights reserved. Preliminary data sheet Rev. 1.01 -- 15 November 2007 33 of 68 D R A FT NXP Semiconductors LPC2917/19 FT FT FT D D R R A A A FT FT FT D D R A FT D R D R R A FT D D R A D R ARM9 microcontroller with CAN and LIN A D R A A FT D R A D R A FT D R A FT A FT D R FT D R A F R ADC2_EXT_START ADC1_EXT_START D D R A FT D R A FT D A FT D R A R pause_0 pause MSCSS(1) TIMER 0 c0 m0 c1 c2 c3 m1 m2 m3 MSCSS(1) TIMER 1 c0 m0 c1 c2 c3 m1 m2 m3 pause PWM0(3) s_i TE_i s_o c_i TE_o trap ADC1(2) st0 st1 st2 so st3 so0 so1 so2 pause_0 ADC2(2) st0 st1 st2 so st3 PWM1(3) s_i TE_i s_o c_i TE_o trap PWM2(3) s_i TE_i s_o c_i TE_o trap PWM3(3) s_i TE_i s_o c_i TE_o trap MSCSS PAUSE PWM0 TRAP PWM1 TRAP PWM2 TRAP PWM3 TRAP 002aad347 (1) Timers: c0 to c3 = capture in 0 to capture in 3 m0 to m3 = match out 0 to match out 3 (2) ADCs: st0 to st3 = start 0 to start 3 inputs s0 to s3 = sync_out 0 to sync_out 3 (3) PWMs: c_i = carrier in s_i = sync_in s_o = sync_out TE_i = trans_enable_in TE_o = trans_enable_out Fig 8. Modulation and sampling-control subsystem synchronization and triggering 8.7.3 MSCSS pin description The pins of the LPC2917/19 MSCSS associated with the two ADC modules are described in Section 8.7.5.3. Pins directly connected to the four PWM modules are described in Section 8.7.6.5: pins directly connected to the MSCSS timer 1 module are described in Section 8.7.7.3. 8.7.4 MSCSS clock description The MSCSS is clocked from a number of different sources: LPC2917_19_1 (c) NXP B.V. 2007. All rights reserved. Preliminary data sheet Rev. 1.01 -- 15 November 2007 34 of 68 D R A FT NXP Semiconductors LPC2917/19 FT FT FT D D R R A A A FT FT FT D D R A FT D R R A FT D D D R A D R ARM9 microcontroller with CAN and LIN A D R A D R A D D R A FT A FT D R FT R * * * * CLK_SYS_MSCSS_A clocks the AHB side of the AHB-to-VPB bus bridge R A FT D R A FT F R A CLK_MSCSS_VPB clocks the subsystem VPB bus CLK_MSCSS_MTMR0/1 clocks the timers CLK_MSCSS_PWM0..3 clocks the PWMs. D Each ADC has two clock areas; a VPB part clocked by CLK_MSCSS_ADCx_VPB (x = 1 or 2) and a control part for the analog section clocked by CLK_ADCx = 1 or 2), see Section 7.2.2. All clocks are derived from the BASE_MSCSS_CLK, except for CLK_SYS_MSCSS_A which is derived form BASE_SYS_CLK, and the CLK_ADCx clocks which are derived from BASE_CLK_ADC. If specific PWM or ADC modules are not used their corresponding clocks can be switched off. D R A FT D R A FT D A FT D R A R 8.7.5 Analog-to-digital converter 8.7.5.1 Overview The MSCSS in the LPC2917/19 includes two 10-bit successive-approximation analog-to-digital converters. The key features of the ADC interface module are: * ADC1 and ADC2: Eight analog inputs; time-multiplexed; measurement range up to 3.3 V * External reference-level inputs * 400 ksamples per second at 10-bit resolution up to 1500 ksamples per second at 2-bit resolution * Programmable resolution from 2-bit to 10-bit * Single analog-to-digital conversion scan mode and continuous analog-to-digital conversion scan mode * Optional conversion on transition on external start input, timer capture/match signal, PWM_sync or `previous' ADC * Converted digital values are stored in a register for each channel * Optional compare condition to generate a `less than' or an `equal to or greater than' compare-value indication for each channel * Power-down mode 8.7.5.2 Description The ADC block diagram, Figure 9, shows the basic architecture of each ADC. The ADC functionality is divided into two major parts; one part running on the MSCSS Subsystem clock, the other on the ADC clock. This split into two clock domains affects the behavior from a system-level perspective. The actual analog-to-digital conversions take place in the ADC clock domain, but system control takes place in the system clock domain. A mechanism is provided to modify configuration of the ADC and control the moment at which the updated configuration is transferred to the ADC domain. LPC2917_19_1 (c) NXP B.V. 2007. All rights reserved. Preliminary data sheet Rev. 1.01 -- 15 November 2007 35 of 68 D R A FT NXP Semiconductors LPC2917/19 FT FT FT D D R R A A A FT FT FT D D R A FT D R D R R A FT D D R A D R ARM9 microcontroller with CAN and LIN A The ADC clock is limited to 4.5 MHz maximum frequency and should always be lower than or equal to the system clock frequency. To meet this constraint or to select the desired lower sampling frequency the clock generation unit provides a programmable fractional system-clock divider dedicated to the ADC clock. Conversion rate is determined by the ADC clock frequency divided by the number of resolution bits plus one. Accessing ADC registers requires an enabled ADC clock, which is controllable via the clock generation unit, see Section 8.8.4. R A Each ADC has four start inputs. Note that start 0 and start 2 are captured in the system clock domain while start 1 and start 3 are captured in the ADC domain. The start inputs are connected at MSCSS level, see Section 8.7.2.1 for details. D R A A FT D R A D FT D R A FT D R D R A FT A FT D R FT D R A F R A FT D FT D R A D A R CLK_ADCx_VPB (MSCSS SubSystem clock) VPB SubSystem domain CLK_ADCx (ADC clock) (upto 4.5 MHz) ADC domain update VPB system bus ADC control & registers Conversion data Config data ADC control & registers 3.3 V Analog to Digital convertor Analog mux Analog inputs ADC1: 8 ADC2: 8 ADC IRQ IRQ Start 0 Start 2 Start 1 Start 3 Sync_out 001aad331 ** Fig 9. ADC block diagram 8.7.5.3 ADC pin description The two ADC modules in the MSCSS have the pins described below. The ADCx input pins are combined with other functions on the port pins of the LPC2917/19. The VREFN and VREFP pins are common for both ADCs. Table 20 shows the ADC pins. Table 20. Symbol ADCn IN[7:0] ADCn_EXT_START VREFN VREFP Analog to digital converter pins Direction in in in in Description analog input for ADCn, channel 7 to channel 0 (n is 1 or 2) ADC external start-trigger input (n is 1 or 2) ADC LOW reference level ADC HIGH reference level LPC2917_19_1 (c) NXP B.V. 2007. All rights reserved. Preliminary data sheet Rev. 1.01 -- 15 November 2007 36 of 68 D R A FT NXP Semiconductors LPC2917/19 FT FT FT D D R R A A A FT FT FT D D R A FT D R R A FT D D D R A D R ARM9 microcontroller with CAN and LIN A D R A D R A D D R A FT A FT D R FT R 8.7.5.4 ADC clock description D R The ADC modules are clocked from two different sources; CLK_MSCSS_ADCx_VPB and CLK_ADCx (x = 1 or 2), see Section 7.2.2. Note that each ADC has its own CLK_ADCx and CLK_MSCSS_ADCx_VPB branch clocks for power management. If an ADC is unused both its CLK_MSCSS_ADCx_VPB and CLK_ADCx can be switched off. The frequency of all the CLK_MSCSS_ADCx_VPB clocks is identical to CLK_MSCSS_VPB since they are derived from the same base clock BASE_MSCSS_CLK. Likewise the frequency of all the CLK_ADCx clocks is identical since they are derived from the same base clock BASE_ADC_CLK. The register interface towards the system bus is clocked by CLK_MSCSS_ADCx_VPB. Control logic for the analog section of the ADC is clocked by CLK_ADCx, see also Figure 9. D R A FT D R A FT R A F D R A FT D FT D R A R A A FT 8.7.6 PWM 8.7.6.1 Overview The MSCSS in the LPC2917/19 includes four PWM modules with the following features. * * * * * * Six pulse-width modulated output signals Double edge features (rising and falling edges programmed individually) Optional interrupt generation on match (each edge) Different operation modes: continuous or run-once 16-bit PWM counter and 16-bit prescale counter allow a large range of PWM periods A protective mode (TRAP) holding the output in a software-controllable state and with optional interrupt generation on a trap event a capture event * Three capture registers and capture trigger pins with optional interrupt generation on * Interrupt generation on match event, capture event, PWM counter overflow or trap event * A burst mode mixing the external carrier signal with internally generated PWM * Programmable sync-delay output to trigger other PWM modules (master/slave behavior) 8.7.6.2 Description The ability to provide flexible waveforms allows PWM blocks to be used in multiple applications; e.g. automotive dimmer/lamp control and fan control. Pulse-width modulation is the preferred method for regulating power since no additional heat is generated and it is energy-efficient when compared with linear-regulating voltage control networks. The PWM delivers the waveforms/pulses of the desired duty cycles and cycle periods. A very basic application of these pulses can be in controlling the amount of power transferred to a load. Since the duty cycle of the pulses can be controlled, the desired amount of power can be transferred for a controlled duration. Two examples of such applications are: LPC2917_19_1 (c) NXP B.V. 2007. All rights reserved. Preliminary data sheet Rev. 1.01 -- 15 November 2007 37 of 68 D R A FT NXP Semiconductors LPC2917/19 FT FT FT D D R R A A A FT FT FT D D R A FT D R D R R A FT D D R A D R ARM9 microcontroller with CAN and LIN A * Automotive dimmer controller: The flexibility of providing waves of a desired duty A FT D R cycle and cycle period allows the PWM to control the amount of power to be transferred to the load. The PWM functions as a dimmer controller in this application * Motor controller: The PWM provides multi-phase outputs, and these outputs can be controlled to have a certain pattern sequence. In this way the force/torque of the motor can be adjusted as desired. This makes the PWM function as a motor drive. FT D R A D R A D R A D R A FT A D R A FT A FT D R FT D R A F R A FT D FT D R A D R Sync_in Transfer_enable_in VPB domain PWM domain update VPB system bus PWM control & registers Capture data PWM counter value Config data IRQ's IRQ pwm IRQ capt_match PWM Counter, prescale counter & shadow registers Match outputs Capture inputs Trap input Carier inputs Sync_out Transfer_enable_out Fig 10. PWM block diagram The PWM block diagram in Figure 10 shows the basic architecture of each PWM. PWM functionality is split into two major parts, a VPB domain and a PWM domain, both of which run on clocks derived from the BASE_MSCSS_CLK. This split into two domains affects behavior from a system-level perspective. The actual PWM and prescale counters are located in the PWM domain but system control takes place in the VPB domain. The actual PWM consists of two counters; a 16-bit prescale counter and a 16-bit PWM counter. The position of the rising and falling edges of the PWM outputs can be programmed individually. The prescale counter allows high system bus frequencies to be scaled down to lower PWM periods. Registers are available to capture the PWM counter values on external events. Note that in the Modulation and Sampling SubSystem, each PWM has its individual clock source CLK_MSCSS_PWMx (x runs from 0 to 3). Both the prescale and the timer counters within each PWM run on this clock CLK_MSCSS_PWMx, and all time references are related to the period of this clock. See Section 8.8 for information on generation of these clocks. 8.7.6.3 Synchronizing the PWM counters A mechanism is included to synchronize the PWM period to other PWMs by providing a sync input and a sync output with programmable delay. Several PWMs can be synchronized using the trans_enable_in/trans_enable_out and sync_in/sync_out ports. See Section 8.7.2.1 for details of the connections of the PWM modules within the MSCSS in the LPC2917/19. PWM 0 can be master over PWM 1; PWM 1 can be master over PWM 2, etc. LPC2917_19_1 (c) NXP B.V. 2007. All rights reserved. Preliminary data sheet Rev. 1.01 -- 15 November 2007 38 of 68 D R A FT NXP Semiconductors LPC2917/19 FT FT FT D D R R A A A FT FT FT D D R A FT D R R A FT D D D R A D R ARM9 microcontroller with CAN and LIN A D R A D R A D D R A FT A FT D R FT R 8.7.6.4 Master and slave mode D R A PWM module can provide synchronization signals to other modules (also called Master mode). The signal sync_out is a pulse of one clock cycle generated when the internal PWM counter (re)starts. The signal trans_enable_out is a pulse synchronous to sync_out, generated if a transfer from system registers to PWM shadow registers occurred when the PWM counter restarted. A delay may be inserted between the counter start and generation of trans_enable_out and sync_out. A PWM module can use input signals trans_enable_in and sync_in to synchronize its internal PWM counter and the transfer of shadow registers (Slave mode). 8.7.6.5 PWM pin description Each of the four PWM modules in the MSCSS has the following pins. These are combined with other functions on the port pins of the LPC2917/19. Table 21 shows the PWM0 to PWM3 pins. Table 21. Symbol PWMn CAP[0] PWMn CAP[1] PWMn CAP[2] PWMn MAT[0] PWMn MAT[1] PWMn MAT[2] PWMn MAT[3] PWMn MAT[4] PWMn MAT[5] PWMn TRAP PWM pins Direction in in in out out out out out out in Description PWM n capture input 0 PWM n capture input 1 PWM n capture input 2 PWM n match output 0 PWM n match output 1 PWM n match output 2 PWM n match output 3 PWM n match output 4 PWM n match output 5 PWM n trap input R A FT D R R A F D R A FT D FT D R A A FT R A A FT D 8.7.6.6 PWM clock description The PWM modules are clocked by CLK_MSCSS_PWMx (x = 0-3), see Section 7.2.2. Note that each PWM has its own CLK_MSCSS_PWMx branch clock for power management. The frequency of all these clocks is identical to CLK_MSCSS_VPB since they are derived from the same base clock BASE_MSCSS_CLK. Also note that unlike the timer modules in the Peripheral SubSystem, the actual timer counter registers of the PWM modules run at the same clock as the VPB system interface CLK_MSCSS_VPB. This clock is independent of the AHB system clock. If a PWM module is not used its CLK_MSCSS_PWMx branch clock can be switched off. 8.7.7 Timers in the MSCSS 8.7.7.1 Overview The two timers in the MSCSS are functionally identical to the timers in the peripheral subsystem, see Section 8.4.3. The features of the timers in the MSCSS are the same as the timers in the peripheral subsystem, but the capture inputs and match outputs are not available on the device pins. These signals are instead connected to the ADC and PWM modules as outlined in the description of the MSCSS, see Section 8.7.2. LPC2917_19_1 (c) NXP B.V. 2007. All rights reserved. Preliminary data sheet Rev. 1.01 -- 15 November 2007 39 of 68 D R A FT NXP Semiconductors LPC2917/19 FT FT FT D D R R A A A FT FT FT D D R A FT D R R A FT D D D R A D R ARM9 microcontroller with CAN and LIN A D R A D R A D D R A FT A FT D R FT R 8.7.7.2 Description See section Section 8.4.3.2 for a description of the timers. D R R A FT D R R A F D R A A FT A 8.7.7.3 MSCSS timer-pin description MSCSS timer 0 has no external pins. FT D R A FT D R A MSCSS timer 1 has a PAUSE pin available as external pin. The PAUSE pin is combined with other functions on the port pins of the LPC2917/19. Table 22 shows the MSCSS timer 1 external pin. Table 22. Symbol MSCSS PAUSE MSCSS timer 1 pin Direction in Description pause pin for MSCSS timer 1 FT D 8.7.7.4 MSCSS timer-clock description The Timer modules in the MSCSS are clocked by CLK_MSCSS_MTMRx (x = 0-1), see Section 7.2.2. Note that each timer has its own CLK_MSCSS_MTMRx branch clock for power management. The frequency of all these clocks is identical to CLK_MSCSS_VPB since they are derived from the same base clock BASE_MSCSS_CLK. Note that, unlike the timer modules in the Peripheral SubSystem, the actual timer counter registers run at the same clock as the VPB system interface CLK_MSCSS_VPB. This clock is independent of the AHB system clock. If a timer module is not used its CLK_MSCSS_MTMRx branch clock can be switched off. 8.8 Power, clock and reset control subsystem 8.8.1 Overview The Power, Clock and Reset Control Subsystem (PCRSS) in the LPC2917/19 includes a Clock Generator Unit (CGU), a Reset Generator Unit (RGU) and a Power Management Unit (PMU). 8.8.2 Description Figure 11 provides an overview of the PCRSS. An AHB-to-DTL bridge takes care of communication with the AHB system bus. LPC2917_19_1 (c) NXP B.V. 2007. All rights reserved. Preliminary data sheet Rev. 1.01 -- 15 November 2007 40 of 68 D R A FT NXP Semiconductors LPC2917/19 FT FT FT D D R R A A A FT FT FT D D R A FT D R D R R A FT D D R A D R ARM9 microcontroller with CAN and LIN A D R A A FT D R A D R A FT D R A FT A FT D R FT D R A F R xo 50 m _ou t xo5 0m _in Power, Clock & Reset D D R A FT D R A FT D A R CGU Xtal Oscillator PLL out0 out1 ... out9 C lo ck Ga te s FT PMU base clocks D R A Low Power Ring Oscillator (Ringo) branch clocks CGU registers C lock E na ble C on trol FDIV[6:0] AHB Master Disable Grant AHB Master Disable Req PM U _reg AHB2DTL Bridge RGU wakeup_a RGU registers AHB_RST ... ... SCU_RST Reset Output Delay Logic WARM_RST COLD_RST PCR_RST RGU_RST POR_RST POR Input Deglitch/ Sync RSTN (device pin) Reset from Watchdog counter Fig 11. PCRSS block diagram 8.8.3 PCR subsystem clock description The PCRSS is clocked by a number of different clocks. CLK_SYS_PCRSS clocks the AHB side of the AHB to DTL bus bridge and CLK_PCR_SLOW clocks the CGU, RGU and PMU internal logic, see Section 7.2.2. CLK_SYS_PCRSS is derived from BASE_SYS_CLK, which can be switched off in low-power modes. CLK_PCR_SLOW is derived from BASE_PCR_CLK and is always on in order to be able to wake up from low-power modes. 8.8.4 Clock Generation Unit (CGU) 8.8.4.1 Overview The key features are: LPC2917_19_1 (c) NXP B.V. 2007. All rights reserved. Preliminary data sheet Rev. 1.01 -- 15 November 2007 41 of 68 D R A FT NXP Semiconductors LPC2917/19 FT FT FT D D R R A A A FT FT FT D D R A FT D R D R R A FT D D R A D R ARM9 microcontroller with CAN and LIN A * Generation of 10 and 2 test-base clocks, selectable from several embedded clock A D R A D R A D R A D R A FT A FT D R FT D R A R sources FT D F FT D * * * * * * * * * Crystal oscillator with power-down Control PLL with power-down Very low-power ring oscillator, always on to provide a 'safe clock' Seven fractional clock dividers with L/D division Individual source selector for each base clock, with glitch-free switching Autonomous clock-activity detection on every clock source Protection against switching to invalid or inactive clock sources Embedded frequency counter R Register write-protection mechanism to prevent unintentional alteration of clocks Remark: Any clock-frequency adjustment has a direct impact on the timing of on-board peripherals such as the UARTs, SPI, watchdog, timers, CAN controller, LIN master controller, ADCs or flash-memory interface. 8.8.4.2 Description The clock generation unit provides 10 internal clock sources as described in Table 23. Table 23. CGU base clocks Frequency (MHz) [1] 0.4 80 0.4 80 80 80 40 80 4.5 [2] R A FT D R A FT D A FT D R A Number Name 0 1 2 3 4 5 6 7 8 [1] [2] Description Base safe clock (always on) Base system clock Base PCR subsystem clock Base IVNSS subsystem clock Base MSCSS subsystem clock Base UART clock Base SPI clock Base timers clock Base ADCs clock BASE_SAFE_CLK BASE_SYS_CLK BASE_PCR_CLK BASE_IVNSS_CLK BASE_MSCSS_CLK BASE_UART_CLK BASE_SPI_CLK BASE_TMR_CLK BASE_ADC_CLK Maximum frequency that guarantees stable operation of the LPC2917/19. Fixed to low-power oscillator. For generation of these base clocks, the CGU consists of primary and secondary clock generators and one output generator for each base clock. LPC2917_19_1 (c) NXP B.V. 2007. All rights reserved. Preliminary data sheet Rev. 1.01 -- 15 November 2007 42 of 68 D R A FT NXP Semiconductors LPC2917/19 FT FT FT D D R R A A A FT FT FT D D R A FT D R D R R A FT D D R A D R ARM9 microcontroller with CAN and LIN A D R A A FT D R A D R A FT D R D R A FT A FT D R FT D R A F R D R Clock Source Bus LP_OSC A A FT D R A FT D FT Xtal Oscilator D PLL FDIV0 OUT 0 R A FDIV1 OUT 1 FDIV6 OUT 9 Frequency Monitor Clock Detection DTL MMIO Interface Fig 12. Block diagram of the CGU There are two primary clock generators: a low-power ring oscillator (LP_OSC) and a crystal oscillator. See Figure 12. LP_OSC is the source for the BASE_PCR_CLK that clocks the CGU itself and for BASE_SAFE_CLK that clocks a minimum of other logic in the device (like the watchdog timer). To prevent the device from losing its clock source LP_OSC cannot be put into power-down. The crystal oscillator can be used as source for high-frequency clocks or as an external clock input if a crystal is not connected. Secondary clock generators are a PLL and seven fractional dividers (FDIV0..6). The PLL has three clock outputs: normal, 120 phase-shifted and 240 phase-shifted. Configuration of the CGU: For every output generator - generating the base clocks - a choice can be made from the primary and secondary clock generators according to Figure 13. LPC2917_19_1 (c) NXP B.V. 2007. All rights reserved. Preliminary data sheet Rev. 1.01 -- 15 November 2007 43 of 68 D R A FT NXP Semiconductors LPC2917/19 FT FT FT D D R R A A A FT FT FT D D R A FT D R D R R A FT D D R A D R ARM9 microcontroller with CAN and LIN A D R A A FT D R A D R A FT D R A D R A FT A FT D R FT D R A F R A D R OSC1M FDIV0..6 XO50M FT D R A FT D R A FT D PLL160M clkout / clkout120 / clkout240 Output Control Clock outputs Fig 13. Structure of the clock generation scheme Any output generator (except for BASE_SAFE_CLK and BASE_PCR_CLK) can be connected to either a fractional divider (FDIV0..6) or to one of the outputs of the PLL or to LP_OSC/crystal oscillator directly. BASE_SAFE_CLK and BASE_PCR_CLK can use only LP_OSC as source. The fractional dividers can be connected to one of the outputs of the PLL or directly to LP_OSC/crystal Oscillator. The PLL can be connected to the crystal oscillator. In this way every output generating the base clocks can be configured to get the required clock. Multiple output generators can be connected to the same primary or secondary clock source, and multiple secondary clock sources can be connected to the same PLL output or primary clock source. Invalid selections/programming - connecting the PLL to an FDIV or to one of the PLL outputs itself for example - will be blocked by hardware. The control register will not be written, the previous value will be kept, although all other fields will be written with new data. This prevents clocks being blocked by incorrect programming. Default Clock Sources: Every secondary clock generator or output generator is connected to LP_OSC at reset. In this way the device runs at a low frequency after reset. It is recommended to switch BASE_SYS_CLK to a high-frequency clock generator as (one of) the first step(s) in the boot code after verifying that the high-frequency clock generator is running. LPC2917_19_1 (c) NXP B.V. 2007. All rights reserved. Preliminary data sheet Rev. 1.01 -- 15 November 2007 44 of 68 D R A FT NXP Semiconductors LPC2917/19 FT FT FT D D R R A A A FT FT FT D D R A FT D R D R R A FT D D R A D R ARM9 microcontroller with CAN and LIN A Clock Activity Detection: Clocks that are inactive are automatically regarded as invalid, and values of 'CLK_SEL' that would select those clocks are masked and not written to the control registers. This is accomplished by adding a clock detector to every clock generator. The RDET register keeps track of which clocks are active and inactive, and the appropriate `CLK_SEL' values are masked and unmasked accordingly. Each clock detector can also generate interrupts at clock activation and deactivation so that the system can be notified of a change in internal clock status. R A A FT D R A FT D Clock detection is done using a counter running at the BASE_PCR_CLK frequency. If no positive clock edge occurs before the counter has 32 cycles of BASE_PCR_CLK the clock is assumed to be inactive. As BASE_PCR_CLK is slower than any of the clocks to be detected, normally only one BASE_PCR_CLK cycle is needed to detect activity. After reset all clocks are assumed to be `non-present', so the RDET status register will be correct only after 32 BASE_PCR_CLK cycles. Note that this mechanism cannot protect against a currently-selected clock going from active to inactive state. Therefore an inactive clock may still be sent to the system under special circumstances, although an interrupt can still be generated to notify the system. Glitch-Free Switching: Provisions are included in the CGU to allow clocks to be switched glitch-free, both at the output generator stage and also at secondary source generators. In the case of the PLL the clock will be stopped and held low for long enough to allow the PLL to stabilize and lock before being re-enabled. For all non-PLL Generators the switch will occur as quickly as possible, although there will always be a period when the clock is held low due to synchronization requirements. If the current clock is high and does not go low within 32 cycles of BASE_PCR_CLK it is assumed to be inactive and is asynchronously forced low. This prevents deadlocks on the interface. 8.8.4.3 PLL functional description A block diagram of the PLL is shown in Figure 14. The input clock is fed directly to the analog section. This block compares the phase and frequency of the inputs and generates the main clock2. These clocks are either divided by 2*P by the programmable post divider to create the output clock, or sent directly to the output. The main output clock is then divided by M by the programmable feedback divider to generate the feedback clock. The output signal of the analog section is also monitored by the lock detector to signal when the PLL has locked onto the input clock. D R A D R A D FT R D R A FT A FT D R FT D R A F R A FT D FT D R A D A R 2. Generation of the main clock is restricted by the frequency range of the PLL clock input. See Table 31, Dynamic characteristics. (c) NXP B.V. 2007. All rights reserved. LPC2917_19_1 Preliminary data sheet Rev. 1.01 -- 15 November 2007 45 of 68 D R A FT NXP Semiconductors LPC2917/19 FT FT FT D D R R A A A FT FT FT D D R A FT D R D R R A FT D D R A D R ARM9 microcontroller with CAN and LIN A D R A A FT D R A D R A FT D R A FT A FT D R FT D R A F R PSEL P23EN D D R A FT clkout120 / clkout240 R A FT Input clock CCO / 2PDIV P23 D D R A FT clkout Bypass Direct / MDIV D R A MSEL Fig 14. PLL block diagram Triple output phases For applications that require multiple clock phases two additional clock outputs can be enabled by setting register P23EN to '1', thus giving three clocks with a 120 phase difference. In this mode all three clocks generated by the analog section are sent to the output dividers. When the PLL has not yet achieved lock the second and third phase output dividers run unsynchronized, which means that the phase relation of the output clocks is unknown. When the PLL LOCK register is set the second and third phase of the output dividers are synchronized to the main output clock CLKOUT PLL, thus giving three clocks with a 120 phase difference. Direct output mode In normal operating mode (with DIRECT set to '0') the CCO clock is divided by 2, 4, 8 or 16 depending on the value on the PSEL[1:0] input, giving an output clock with a 50% duty cycle. If a higher output frequency is needed the CCO clock can be sent directly to the output by setting DIRECT to '1'. Since the CCO does not directly generate a 50% duty cycle clock, the output clock duty cycle in this mode can deviate from 50%. Power-down control A power-down mode has been incorporated to reduce power consumption when the PLL clock is not needed. This is enabled by setting the PD control register bit. In this mode the analog section of the PLL is turned off, the oscillator and the phase-frequency detector are stopped and the dividers enter a reset state. While in power-down mode the LOCK output is low, indicating that the PLL is not in lock. When power-down mode is terminated by clearing the PD control-register bit the PLL resumes normal operation, and makes the LOCK signal high once it has regained lock on the input clock. 8.8.4.4 CGU pin description The CGU module in the LPC2917/19 has the pins listed in Table 24 below. Table 24. Symbol XOUT_OSC XIN_OSC CGU pins Direction out in Description Oscillator crystal output Oscillator crystal input or external clock input LPC2917_19_1 (c) NXP B.V. 2007. All rights reserved. Preliminary data sheet Rev. 1.01 -- 15 November 2007 46 of 68 D R A FT NXP Semiconductors LPC2917/19 FT FT FT D D R R A A A FT FT FT D D R A FT D R R A FT D D D R A D R ARM9 microcontroller with CAN and LIN A D R A D R A D D R A FT A FT D R FT R 8.8.5 Reset Generation Unit (RGU) 8.8.5.1 Overview The key features of the Reset Generation Unit (RGU) are: D R R A FT D R R A F D R A FT A FT A FT D R D * * * * 8.8.5.2 Reset controlled individually per subsystem Automatic reset stretching and release Monitor function to trace resets back to source Register write-protection mechanism to prevent unintentional resets A FT D R A Description The RGU controls all internal resets. Each reset output is defined as a (combination of) reset input sources including the external reset input pins and internal power-on reset, see Table 25. The first five resets listed in this table form a sort of cascade to provide the multiple levels of impact that a reset may have. The combined input sources are logically OR-ed together so that activating any of the listed reset sources causes the output to go active. Table 25. POR_RST RGU_RST PCR_RST COLD_RST WARM_RST SCU_RST CFID_RST FMC_RST EMC_RST SMC_RST GESS_A2V_RST PESS_A2V_RST GPIO_RST UART_RST TMR_RST SPI_RST IVNSS_A2V_RST IVNSS_CAN_RST IVNSS_LIN_RST MSCSS_A2V_RST MSCSS_PWM_RST MSCSS_ADC_RST MSCSS_TMR_RST VIC_RST AHB_RST Reset output configuration Reset Source power-on reset module POR_RST, RSTN pin PCR_RST COLD_RST COLD_RST COLD_RST COLD_RST COLD_RST COLD_RST WARM_RST WARM_RST WARM_RST WARM_RST WARM_RST WARM_RST WARM_RST WARM_RST WARM_RST WARM_RST WARM_RST WARM_RST WARM_RST WARM_RST WARM_RST parts of the device reset when activated LP_OSC; is source for RGU_RST RGU internal; is source for PCR_RST parts with COLD_RST as reset source below parts with WARM_RST as reset source below SCU CFID embedded Flash-Memory Controller (FMC) embedded SRAM-Memory Controller external Static-Memory Controller (SMC) GeSS AHB-to-VPB bridge PeSS AHB-to-VPB bridge all GPIO modules all UART modules all Timer modules in PeSS all SPI modules IVNSS AHB-to-VPB bridge all CAN modules including Acceptance filter all LIN modules MSCSS AHB to VPB bridge all PWM modules all ADC modules all Timer modules in MSCSS Vectored Interrupt Controller (VIC) CPU and AHB Multilayer Bus infrastructure (c) NXP B.V. 2007. All rights reserved. Reset Output RGU_RST, WATCHDOG PCR internal; is source for COLD_RST LPC2917_19_1 Preliminary data sheet Rev. 1.01 -- 15 November 2007 47 of 68 D R A FT NXP Semiconductors LPC2917/19 FT FT FT D D R R A A A FT FT FT D D R A FT D R R A FT D D D R A D R ARM9 microcontroller with CAN and LIN A D R A D R A D D R A FT A FT D R FT R 8.8.5.3 RGU pin description D R The RGU module in the LPC2917/19 has the following pins. Table 26 shows the RGU pins. D R A Table 26. Symbol RSTN RGU pins Directio Description n IN external reset input, Active LOW; pulled up internally R A FT R A F D R A FT D R A FT D R A A FT D FT 8.8.6 Power Management Unit (PMU) 8.8.6.1 Overview This module enables software to actively control the system's power consumption by disabling clocks not required in a particular operating mode. Using the base clocks from the CGU as input, the PMU generates branch clocks to the rest of the LPC2917/19. Output clocks branched from the same base clock are phaseand frequency-related. These branch clocks can be individually controlled by software programming. The key features are: * * * * * * * 8.8.6.2 Individual clock control for all LPC2917/19 sub-modules Activates sleeping clocks when a wake-up event is detected Clocks can be individually disabled by software Supports AHB master-disable protocol when AUTO mode is set Disables wake-up of enabled clocks when power-down mode is set Activates wake-up of enabled clocks when a wake-up event is received Status register is available to indicate if an input base clock can be safely switched off (i.e. all branch clocks are disabled) Description The PMU controls all internal clocks of the device for power-mode management. With some exceptions, each branch clock can be switched on or off individually under control of software register bits located in its individual configuration register. Some branch clocks controlling vital parts of the device operate in a fixed mode. Table 27 shows which modecontrol bits are supported by each branch clock. By programming the configuration register the user can control which clocks are switched on or off, and which clocks are switched off when entering power-down mode. Note that the standby-wait-for-interrupt instructions of the ARM968E-S processor (putting the ARM CPU into a low-power state) are not supported. Instead putting the ARM CPU into power-down should be controlled by disabling the branch clock for the CPU. Remark: For any disabled branch clocks to be re-activated their corresponding base clocks must be running (controlled by the CGU). Table 27 shows the relation between branch and base clocks, see also Section 7.2.1. Every branch clock is related to one particular base clock: it is not possible to switch the source of a branch clock in the PMU. LPC2917_19_1 (c) NXP B.V. 2007. All rights reserved. Preliminary data sheet Rev. 1.01 -- 15 November 2007 48 of 68 D R A FT NXP Semiconductors LPC2917/19 FT FT FT D D R R A A A FT FT FT D D D R R R A A FT FT D D D R A D R ARM9 microcontroller with CAN and LIN A Table 27. Branch clock overview Legend: "1" Indicates that the related register bit is tied off to logic HIGH, all writes are ignored "0" Indicates that the related register bit is tied off to logic LOW, all writes are ignored "+" Indicates that the related register bit is readable and writable Branch Clock Name Base Clock Implemented Switch On/Off Mechanism WAKEUP AUTO 0 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + RUN 1 1 1 1 + + + + + + + + + + + + + + + 1 + + + + + + + + + + + + + + + + 0 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + D R A R A FT D R A D R A FT D R A FT D R D R A FT A FT D R FT D R A F R A FT D A FT D R A D R CLK_SAFE CLK_SYS_CPU CLK_SYS CLK_SYS_PCR CLK_SYS_FMC CLK_SYS_RAM0 CLK_SYS_RAM1 CLK_SYS_SMC CLK_SYS_GESS CLK_SYS_VIC CLK_SYS_PESS CLK_SYS_GPIO0 CLK_SYS_GPIO1 CLK_SYS_GPIO2 CLK_SYS_GPIO3 CLK_SYS_IVNSS_A CLK_SYS_MSCSS_A CLK_SYS_CHCA CLK_SYS_CHCB CLK_PCR_SLOW CLK_IVNSS_VPB CLK_IVNSS_CANC0 CLK_IVNSS_CANC1 CLK_IVNSS_LIN0 CLK_IVNSS_LIN1 CLK_MSCSS_VPB CLK_MSCSS_MTMR0 CLK_MSCSS_MTMR1 CLK_MSCSS_PWM0 CLK_MSCSS_PWM1 CLK_MSCSS_PWM2 CLK_MSCSS_PWM3 BASE_SAFE_CLK BASE_SYS_CLK BASE_SYS_CLK BASE_SYS_CLK BASE_SYS_CLK BASE_SYS_CLK BASE_SYS_CLK BASE_SYS_CLK BASE_SYS_CLK BASE_SYS_CLK BASE_SYS_CLK BASE_SYS_CLK BASE_SYS_CLK BASE_SYS_CLK BASE_SYS_CLK BASE_SYS_CLK BASE_SYS_CLK BASE_SYS_CLK BASE_SYS_CLK BASE_PCR_CLK BASE_IVNSS_CLK BASE_IVNSS_CLK BASE_IVNSS_CLK BASE_IVNSS_CLK BASE_IVNSS_CLK BASE_MSCSS_CLK BASE_MSCSS_CLK BASE_MSCSS_CLK BASE_MSCSS_CLK BASE_MSCSS_CLK BASE_MSCSS_CLK BASE_MSCSS_CLK CLK_MSCSS_ADC1_VPB BASE_MSCSS_CLK CLK_MSCSS_ADC2_VPB BASE_MSCSS_CLK CLK_UART0 CLK_UART1 LPC2917_19_1 BASE_UART_CLK BASE_UART_CLK (c) NXP B.V. 2007. All rights reserved. Preliminary data sheet Rev. 1.01 -- 15 November 2007 49 of 68 D R A FT NXP Semiconductors LPC2917/19 FT FT FT D D R R A A A FT FT FT D D D R R R A A FT FT D D D R A D R ARM9 microcontroller with CAN and LIN A Table 27. Branch clock overview ...continued Legend: "1" Indicates that the related register bit is tied off to logic HIGH, all writes are ignored "0" Indicates that the related register bit is tied off to logic LOW, all writes are ignored "+" Indicates that the related register bit is readable and writable Branch Clock Name Base Clock Implemented Switch On/Off Mechanism WAKEUP AUTO + + + + + + + + + 0 RUN + + + + + + + + + 1 + + + + + + + + + 0 D R A R A FT D R A D R A FT D R A FT D R D R A FT A FT D R FT D R A F R A FT D A FT D R A D R CLK_SPI0 CLK_SPI1 CLK_SPI2 CLK_TMR0 CLK_TMR1 CLK_TMR2 CLK_TMR3 CLK_ADC1 CLK_ADC2 CLK_TESTSHELL_IP BASE_SPI_CLK BASE_SPI_CLK BASE_SPI_CLK BASE_TMR_CLK BASE_TMR_CLK BASE_TMR_CLK BASE_TMR_CLK BASE_ADC_CLK BASE_ADC_CLK BASE_CLK_TESTSHELL 8.8.6.3 PMU pin description The PMU has no external pins. 8.9 Vectored interrupt controller 8.9.1 Overview The LPC2917/19 contains a very flexible and powerful Vectored Interrupt Controller (VIC) to interrupt the ARM processor on request. The key features are: * * * * * * Level-active interrupt request with programmable polarity 56 interrupt-request inputs Software-interrupt request capability associated with each request input Observability of interrupt-request state before masking Software-programmable priority assignments to interrupt requests up to 15 levels Software-programmable routing of interrupt requests towards the ARM-processor inputs IRQ and FIQ * Fast identification of interrupt requests through vector * Support for nesting of interrupt service routines 8.9.2 Description The Vectored Interrupt Controller routes incoming interrupt requests to the ARM processor. The interrupt target is configured for each interrupt request input of the VIC. The targets are defined as follows: * Target 0 is ARM processor FIQ (fast interrupt service) * Target 1 is ARM processor IRQ (standard interrupt service) LPC2917_19_1 (c) NXP B.V. 2007. All rights reserved. Preliminary data sheet Rev. 1.01 -- 15 November 2007 50 of 68 D R A FT NXP Semiconductors LPC2917/19 FT FT FT D D R R A A A FT FT FT D D R A FT D R D R R A FT D D R A D R ARM9 microcontroller with CAN and LIN A Interrupt-request masking is performed individually per interrupt target by comparing the priority level assigned to a specific interrupt request with a target-specific priority threshold. The priority levels are defined as follows: R A * Priority level 0 corresponds to `masked' (i.e. interrupt requests with priority 0 never lead to an interrupt) D R A A FT D R A D FT D R A FT D R D R A FT A FT D R FT D R A F R A FT D A FT D R * Priority 1 corresponds to the lowest priority * Priority 15 corresponds to the highest priority Software interrupt support is provided and can be supplied for: D R A * Testing RTOS interrupt handling without using device-specific interrupt service routines * Software emulation of an interrupt-requesting device, including interrupts 8.9.3 VIC pin description The VIC module in the LPC2917/19 has no external pins. 8.9.4 VIC clock description The VIC is clocked by CLK_SYS_VIC, see Section 7.2.2. 9. Limiting values Table 28. Limiting values In accordance with the Absolute Maximum Rating System (IEC 60134). Symbol Supply pins Ptot VDD(CORE) VDD(OSC_PLL) VDD(ADC3V3) VDD(IO) IDD ISS Total power dissipation. Core supply voltage. Oscillator and PLL supply voltage. 3.3 V ADC supply voltage. I/O digital supply voltage. Supply current. Ground current. Average value per supply pin. Average value per ground pin. [2] [1] Parameter Conditions Min -0.5 -0.5 -0.5 -0.5 - Max 1 +2.0 +2.0 +4.6 +4.6 98 98 Unit W V V V V mA mA [2] Input pins and I/O pins VXIN_OSC VXIN_RTC VI(IO) VI(ADC) VVREFP VVREFN II(ADC) Voltage on pin XIN_OSC. Voltage on pin XIN_RTC. I/O input voltage. ADC input voltage. Voltage on pin VREFP. Voltage on pin VREFN. ADC input current. Average value per input pin. [2] [3][4][5] -0.5 -0.5 -0.5 -0.5 -0.5 -0.5 I/O port 0. [4][5] +2.0 +2.0 VDD(IO) + 3.0 VDD(ADC3V3) + 0.5 +3.6 +3.6 35 V V V V V V mA Output pins and I/O pins configured as output LPC2917_19_1 (c) NXP B.V. 2007. All rights reserved. Preliminary data sheet Rev. 1.01 -- 15 November 2007 51 of 68 D R A FT NXP Semiconductors LPC2917/19 FT FT FT D D R R A A A FT FT FT D D R A FT D R R A FT D D D R A D R ARM9 microcontroller with CAN and LIN A D R A D R A D D R A FT A FT D R FT R Table 28. Limiting values ...continued In accordance with the Absolute Maximum Rating System (IEC 60134). Symbol IOHS IOLS General Tstg Tamb Tvj Memory nendu(fl) tret(fl) Endurance of flash memory. Flash memory retention time. Electrostatic discharge voltage. On all pins. Human body model. Machine model. Charged device model. On corner pins. Charged device model. [1] [2] [3] [4] [5] [6] [7] [8] [9] Based on package heat transfer, not device power consumption. Peak current must be limited at 25 times average current. For I/O Port 0, the maximum input voltage is defined by VI(ADC). Only when VDD(IO) is present. Note that pull-up should be off. With pull-up do not exceed 3.6 V. [7] [8] D R R A FT R A F A FT Parameter HIGH-state short-circuit output current. LOW-state short-circuit output current. Storage temperature. Ambient temperature. Virtual junction temperature. Conditions Drive HIGH, output shorted to VSS(IO). Drive LOW, output shorted to VDD(IO). [9] Min - Max -33 +38 Unit D D R R A mA mA A FT D R A FT D [9] FT D R A -40 -40 [6] +150 +85 +125 100 000 20 C C C cycle year -40 - Electrostatic discharge Vesd -2000 -200 -500 -750 +2000 +200 +500 +750 V V V V In accordance with IEC 60747-1. An alternative definition of the virtual junction temperature is: Tvj = Tamb + Ptot x Rth(j-a) where Rth(j-a) is a fixed value; see Section 10. The rating for Tvj limits the allowable combinations of power dissipation and ambient temperature. Human-body model: discharging a 100 pF capacitor via a 10 k series resistor. Machine model: discharging a 200 pF capacitor via a 0.75 H series inductance and 10 resistor. 112 mA per VDD(IO) or VSS(IO) should not be exceeded. 10. Thermal characteristics Table 29. Symbol Rth(j-a) Thermal characteristics Parameter thermal resistance from junction to ambient Conditions in free air package; LQFP144 62 K/W Value Unit LPC2917_19_1 (c) NXP B.V. 2007. All rights reserved. Preliminary data sheet Rev. 1.01 -- 15 November 2007 52 of 68 D R A FT NXP Semiconductors LPC2917/19 FT FT FT D D R R A A A FT FT FT D D R A FT D R R A FT D D D R A D R ARM9 microcontroller with CAN and LIN A D R A D R A D D R A FT A FT D R FT R 11. Static characteristics D R Table 30. Static characteristics VDD(CORE) = VDD(OSC_PLL) ; VDD(IO) = 2.7 V to 3.6 V; VDD(A3V3) = 3.0 V to 3.6 V; Tvj = -40 C to +125 C; all voltages are measured with respect to ground; positive currents flow into the IC; unless otherwise specified.[1] Symbol Supplies Core supply VDD(CORE) IDDD(CORE) Core supply voltage. Core supply current. ARM9 and all peripherals active at max clock speeds. All clocks off. I/O supply VDD(IO) VDD(OSC_PLL) I/O digital supply voltage. Oscillator and PLL supply voltage. 2.7 1.71 1.5 3.0 Normal mode Power-down mode All port pins and VDD(IO) applied except port 0 pins 16 to 31. see Section 9 Port 0 pins 16 to 31. All port pins and VDD(IO) not applied. All other I/O pins, RESET_N, TRST_N, TDI, JTAGSEL, TMS, TCK. VIH HIGH-state input voltage. All port pins, RESET_N, TRST_N, TDI, JTAGSEL, TMS, TCK. All port pins, RESET_N, TRST_N, TDI, JTAGSEL, TMS, TCK. [8] [7][8] [2] R A FT D R R A F D R A FT A FT A FT D R A D Parameter Conditions Min Typ Max Unit FT D R A 1.71 - 1.80 1.1 1.89 2.5 V mA/ MHz A V V mA mA A V mA A V - 30 1.80 3.3 - 450 3.6 1.89 3 1 2 3.6 1.9 4 + 5.5 Oscillator supply IDDD(OSC_PLL) Oscillator and PLL supply start-up current. Normal mode Power-down mode Analog-to-digital converter supply VDD(A3V3) IDDA(A3V3) 3.3 V ADC supply voltage 3.3 V ADC analog supply current. -0.5 Input pins and I/O pins configured as input VI Input voltage. VVREFP -0.5 -0.5 +3.6 VDD(IO) V V 2.0 - - V VIL LOW-state input voltage. - - 0.8 V Vhys ILIH Hysteresis voltage. HIGH-state input leakage current. 0.4 - - 1 V A LPC2917_19_1 (c) NXP B.V. 2007. All rights reserved. Preliminary data sheet Rev. 1.01 -- 15 November 2007 53 of 68 D R A FT NXP Semiconductors LPC2917/19 FT FT FT D D R R A A A FT FT FT D D R A FT D R D R R A FT D D R A D R ARM9 microcontroller with CAN and LIN A Table 30. Static characteristics ...continued VDD(CORE) = VDD(OSC_PLL) ; VDD(IO) = 2.7 V to 3.6 V; VDD(A3V3) = 3.0 V to 3.6 V; Tvj = -40 C to +125 C; all voltages are measured with respect to ground; positive currents flow into the IC; unless otherwise specified.[1] D R A A FT D R A D R A FT D R D R A FT A FT D R FT D R A F R A D R Symbol ILIL II(pd) II(pu) Parameter LOW-state input leakage current. Pull-down input current. Pull-up input current. Conditions Min - Typ 50 -50 Max 1 100 -100 Unit A A FT D R A FT All port pins, VI = 3.3 V; VI = 5.5 V. All port pins, RESET_N, TRST_N, TDI, JTAGSEL, TMS: VI = 0 V; VI > 3.6 V is not allowed. [3] 25 -25 A A FT D D R A Ci VO VOH VOL CL VVREFN VVREFP VI(ADC) Zi Input capacitance. Output voltage. HIGH-state output voltage. Load capacitance. Voltage on pin VREFN. Voltage on pin VREFP. ADC input voltage on port 0 pins Input impedance. Port 0. Between VREFN and VREFP Between VREFN and VDD(A5V) IOH = -4 mA 0 VDD(IO) - 0.4 0 VVREFN + 2 VVREFN 4.4 13.7 2 -1 -1 -20 -20 3 - 8 VDD(IO) 0.4 25 VVREFP - 2 VDD(A3V3) VVREFP 23.6 10 +1 +1 +20 +20 pF V V V pF V V V k k bit LSB LSB mV mV Output pins and I/O pins configured as output LOW-state output voltage. IOL = 4 mA Analog-to-digital converter supply FSR INL DNL Verr(offset) Verr(FS) Full scale range. Integral non-linearity. Differential non-linearity. Offset error voltage. Full-scale error voltage. LPC2917_19_1 (c) NXP B.V. 2007. All rights reserved. Preliminary data sheet Rev. 1.01 -- 15 November 2007 54 of 68 D R A FT NXP Semiconductors LPC2917/19 FT FT FT D D R R A A A FT FT FT D D R A FT D R D R R A FT D D R A D R ARM9 microcontroller with CAN and LIN A Table 30. Static characteristics ...continued VDD(CORE) = VDD(OSC_PLL) ; VDD(IO) = 2.7 V to 3.6 V; VDD(A3V3) = 3.0 V to 3.6 V; Tvj = -40 C to +125 C; all voltages are measured with respect to ground; positive currents flow into the IC; unless otherwise specified.[1] D R A A FT D R A D R A FT D R D R A FT A FT D R FT D R A F R A D R Symbol Oscillator Rs(xtal) Parameter Crystal series resistance. Conditions fosc = 10 MHz to 15 MHz Cxtal = 10 pF; Cext = 18 pF Cxtal = 20 pF; Cext = 39 pF fosc = 15 MHz to 20 MHz Cxtal = 10 pF; Cext = 18 pF [5] [5] Min Typ Max Unit A FT D R A FT D FT D - - 160 60 R A [9] - 80 2 pF Ci Input capacitance of XIN_OSC. High trip-level voltage. Low trip-level voltage. Difference between high and low trip-level voltages. - Power-up reset Vtrip(high) Vtrip(low) Vtrip(dif) [6] [6] [6] 1.2 1.1 50 1.4 1.3 120 1.6 1.5 180 V V mV [1] All parameters are guaranteed over the virtual junction temperature range by design. Pre-testing is performed at Tamb = 125 C on wafer level. Cased products are tested at Tamb = 25 C (final testing). Both pre-testing and final testing use correlated test conditions to cover the specified temperature and power-supply voltage range. Leakage current is exponential to temperature; worst-case value is at 125 C Tvj. All clocks off. Analog modules and FLASH powered down. For Port 0, pin 0 to pin 15 add maximum 1.5 pF for input capacitance to ADC. For Port 0, pin 16 to pin 31 add maximum 1.0 pF for input capacitance to ADC. This value is the minimum drive capability. Maximum short-circuit output current is 33 mA (drive HIGH-level, shorted to ground) or -38 mA. (drive LOW-level, shorted to VDD(IO)). The device will be damaged if multiple outputs are shorted. Cxtal is crystal load capacitance and Cext are the two external load capacitors. The power-up reset has a time filter: VDD(CORE) must be above Vtrip(high) for 2 s before reset is de-asserted; VDD(CORE) must be below Vtrip(low) for 11 s before internal reset is asserted. Not 5 V-tolerant when pull-up is on. For I/O Port 0, the maximum input voltage is defined by VI(ADC). This parameter is not part of production testing or final testing, hence only a typical value is stated. Maximum and minimum values are based on simulation results. [2] [3] [4] [5] [6] [7] [8] [9] 12. Dynamic characteristics Table 31. Dynamic characteristics VDD(CORE) = VDD(OSC_PLL) ; VDD(IO) = 2.7 V to 3.6 V; VDD(A3V3) = 3.0 V to 3.6 V; Tvj = -40 C; all voltages are measured with respect to ground; positive currents flow into the IC; unless otherwise specified. Symbol I/O pins tTHL tTLH HIGH-to-LOW transition time. LOW-to-HIGH transition time. CL = 30 pF CL = 30 pF 4 4 13.8 13.8 ns ns Parameter Conditions Min Typ Max Unit LPC2917_19_1 (c) NXP B.V. 2007. All rights reserved. Preliminary data sheet Rev. 1.01 -- 15 November 2007 55 of 68 D R A FT NXP Semiconductors LPC2917/19 FT FT FT D D R R A A A FT FT FT D D R A FT D R D R R A FT D D R A D R ARM9 microcontroller with CAN and LIN A Table 31. Dynamic characteristics ...continued VDD(CORE) = VDD(OSC_PLL) ; VDD(IO) = 2.7 V to 3.6 V; VDD(A3V3) = 3.0 V to 3.6 V; Tvj = -40 C; all voltages are measured with respect to ground; positive currents flow into the IC; unless otherwise specified. D R A A FT D R A D R A FT D R D R A FT A FT D R FT D R A F R A D R Symbol Internal clock fclk(sys) Parameter System clock frequency. See Table 23. System clock period. See Table 23. RO reference frequency. Start-up time. Conditions Min 10 Typ - Max 80 Unit MHz A FT D R A FT D FT D R A Tclk(sys) 12.5 - 100 ns Low-Power Ring Oscillator fref(RO) tstartup Oscillator fi(osc) Oscillator input frequency. Maximum frequency is the clock input of an external clock source applied to the Xin pin. At maximum frequency. [2] [3] 0.36 At maximum frequency [2]. 0.4 6 0.42 100 MHz s - 10 - 80 MHz tstartup PLL fi(PLL) fo(PLL) Start-up time. - 500 - s PLL input frequency. PLL output frequency. CCO; direct mode. 10 10 156 4 - 25 160 320 4.5 MHz MHz MHz MHz Analog-to-digital converter fi(ADC) fs(max) ADC input frequency. Maximum sampling rate. [4] fi(ADC) = 4.5 MHz; fs = fi(ADC)/(n+1) with n = resolution resolution 2 bit resolution 10 bit 3 2 0.95 95 1 100 38 1500 400 11 10 150 1.05 105 70 63.4 60.3 20.5 ksample/s ksample/s cycles bits s ms ms ns ns ns ns tconv Conversion time. In number of ADC clock cycles. In number of bits. Flash memory tinit twr(pg) ter(sect) tfl(BIST) tacc(clk) tacc(addr) ta(R)int Initialization time. Page write time. Sector erase time. Flash word BIST time. clock access time address access time Internal read-access time. external static memory controller LPC2917_19_1 (c) NXP B.V. 2007. All rights reserved. Preliminary data sheet Rev. 1.01 -- 15 November 2007 56 of 68 D R A FT NXP Semiconductors LPC2917/19 FT FT FT D D R R A A A FT FT FT D D R A FT D R D R R A FT D D R A D R ARM9 microcontroller with CAN and LIN A Table 31. Dynamic characteristics ...continued VDD(CORE) = VDD(OSC_PLL) ; VDD(IO) = 2.7 V to 3.6 V; VDD(A3V3) = 3.0 V to 3.6 V; Tvj = -40 C; all voltages are measured with respect to ground; positive currents flow into the IC; unless otherwise specified. D R A A FT D R A D R A FT D R D R A FT A FT D R FT D R A F R A D R Symbol ta(W)int UART fUART SPI fSPI Parameter Internal write-access time. UART frequency. SPI operating frequency. Conditions Min - Typ - Max 24.9 Unit ns A FT D R A FT D FT D R A 1 65024fclk(uart) 0.4 1 f 2 clk(uart) MHz MHz MHz ns Master operation. Slave operation. [2] 1 65024fclk(spi) 1 65024fclk(spi) 1 f 2 clk(spi) 1 f 4 clk(spi) Jitter Specification CANtjit(cc)(p-p) CAN TXD pin Cycle-to-cycle jitter (peak-to-peak value). 1 [1] All parameters are guaranteed over the virtual junction temperature range by design. Pre-testing is performed at Tamb = 125 C ambient temperature on wafer level. Cased products are tested at Tamb = 25 C (final testing). Both pre-testing and final testing use correlated test conditions to cover the specified temperature and power supply voltage range. This parameter is not part of production testing or final testing, hence only a typical value is stated. Oscillator start-up time depends on the quality of the crystal. For most crystals it takes about 1000 clock pulses until the clock is fully stable. Duty cycle clock should be as close as possible to 50%. [2] [3] [4] LPC2917_19_1 (c) NXP B.V. 2007. All rights reserved. Preliminary data sheet Rev. 1.01 -- 15 November 2007 57 of 68 D R A FT NXP Semiconductors LPC2917/19 FT FT FT D D R R A A A FT FT FT D D R A FT D R R A FT D D D R A D R ARM9 microcontroller with CAN and LIN A D R A D R A D D R A FT A FT D R FT R 13. Package outline LQFP144: plastic low profile quad flat package; 144 leads; body 20 x 20 x 1.4 mm D R R A FT D R R A F D R A FT A FT A FT D R A SOT486-1 D FT D R A c y X A 108 109 73 72 ZE e E HE A A2 A1 (A 3) Lp L detail X wM bp pin 1 index 144 1 wM D HD ZD B vM B 36 bp vM A 37 e 0 5 scale 10 mm DIMENSIONS (mm are the original dimensions) UNIT mm A max. 1.6 A1 0.15 0.05 A2 1.45 1.35 A3 0.25 bp 0.27 0.17 c 0.20 0.09 D (1) 20.1 19.9 E (1) 20.1 19.9 e 0.5 HD HE L 1 Lp 0.75 0.45 v 0.2 w 0.08 y 0.08 Z D(1) Z E(1) 1.4 1.1 1.4 1.1 7 o 0 o 22.15 22.15 21.85 21.85 Note 1. Plastic or metal protrusions of 0.25 mm maximum per side are not included. OUTLINE VERSION SOT486-1 REFERENCES IEC 136E23 JEDEC MS-026 JEITA EUROPEAN PROJECTION ISSUE DATE 00-03-14 03-02-20 Fig 15. Package outline SOT486-1 (LQFP144) LPC2917_19_1 (c) NXP B.V. 2007. All rights reserved. Preliminary data sheet Rev. 1.01 -- 15 November 2007 58 of 68 D R A FT NXP Semiconductors LPC2917/19 FT FT FT D D R R A A A FT FT FT D D R A FT D R R A FT D D D R A D R ARM9 microcontroller with CAN and LIN A D R A D R A D D R A FT A FT D R FT R 14. Soldering 14.1 Introduction D R There is no soldering method that is ideal for all surface mount IC packages. Wave soldering can still be used for certain surface mount ICs, but it is not suitable for fine pitch SMDs. In these situations reflow soldering is recommended. R A FT D R R A F D R A FT A FT A FT D R A D FT D R A 14.2 Through-hole mount packages 14.2.1 Soldering by dipping or by solder wave Typical dwell time of the leads in the wave ranges from 3 seconds to 4 seconds at 250 C or 265 C, depending on solder material applied, SnPb or Pb-free respectively. The total contact time of successive solder waves must not exceed 5 seconds. The device may be mounted up to the seating plane, but the temperature of the plastic body must not exceed the specified maximum storage temperature (Tstg(max)). If the printed-circuit board has been pre-heated, forced cooling may be necessary immediately after soldering to keep the temperature within the permissible limit. 14.2.2 Manual soldering Apply the soldering iron (24 V or less) to the lead(s) of the package, either below the seating plane or not more than 2 mm above it. If the temperature of the soldering iron bit is less than 300 C it may remain in contact for up to 10 seconds. If the bit temperature is between 300 C and 400 C, contact may be up to 5 seconds. 14.3 Surface mount packages 14.3.1 Reflow soldering Key characteristics in reflow soldering are: * Lead-free versus SnPb soldering; note that a lead-free reflow process usually leads to higher minimum peak temperatures (see Figure 16) than a PbSn process, thus reducing the process window * Solder paste printing issues including smearing, release, and adjusting the process window for a mix of large and small components on one board * Reflow temperature profile; this profile includes preheat, reflow (in which the board is heated to the peak temperature) and cooling down. It is imperative that the peak temperature is high enough for the solder to make reliable solder joints (a solder paste characteristic). In addition, the peak temperature must be low enough that the packages and/or boards are not damaged. The peak temperature of the package depends on package thickness and volume and is classified in accordance with Table 32 and 33 LPC2917_19_1 (c) NXP B.V. 2007. All rights reserved. Preliminary data sheet Rev. 1.01 -- 15 November 2007 59 of 68 D R A FT NXP Semiconductors LPC2917/19 FT FT FT D D R R A A A FT FT FT D D R A FT D D R R A FT D D R A D R ARM9 microcontroller with CAN and LIN A D R A D R A D D R A FT A FT D R FT D R Table 32. SnPb eutectic process (from J-STD-020C) Package reflow temperature (C) Volume (mm3) < 350 350 220 220 R R A FT R A F A FT Package thickness (mm) D D R A FT D R A FT D R < 2.5 2.5 Table 33. 235 220 Lead-free process (from J-STD-020C) Package reflow temperature (C) Volume (mm3) < 350 A FT D R A Package thickness (mm) 350 to 2000 260 250 245 > 2000 260 245 245 < 1.6 1.6 to 2.5 > 2.5 260 260 250 Moisture sensitivity precautions, as indicated on the packing, must be respected at all times. Studies have shown that small packages reach higher temperatures during reflow soldering, see Figure 16. temperature maximum peak temperature = MSL limit, damage level minimum peak temperature = minimum soldering temperature peak temperature time 001aac844 MSL: Moisture Sensitivity Level Fig 16. Temperature profiles for large and small components For further information on temperature profiles, refer to Application Note AN10365 "Surface mount reflow soldering description". 14.3.2 Wave soldering Conventional single wave soldering is not recommended for surface mount devices (SMDs) or printed-circuit boards with a high component density, as solder bridging and non-wetting can present major problems. LPC2917_19_1 (c) NXP B.V. 2007. All rights reserved. Preliminary data sheet Rev. 1.01 -- 15 November 2007 60 of 68 D R A FT NXP Semiconductors LPC2917/19 FT FT FT D D R R A A A FT FT FT D D R A FT D R D R R A FT D D R A D R ARM9 microcontroller with CAN and LIN A To overcome these problems the double-wave soldering method was specifically developed. A If wave soldering is used the following conditions must be observed for optimal results: A * Use a double-wave soldering method comprising a turbulent wave with high upward pressure followed by a smooth laminar wave. D R A FT D R A D R A FT D R FT D R D R A FT A FT D R FT D R A F R A FT D A FT D D R * For packages with leads on two sides and a pitch (e): - larger than or equal to 1.27 mm, the footprint longitudinal axis is preferred to be parallel to the transport direction of the printed-circuit board; - smaller than 1.27 mm, the footprint longitudinal axis must be parallel to the transport direction of the printed-circuit board. The footprint must incorporate solder thieves at the downstream end. R A * For packages with leads on four sides, the footprint must be placed at a 45 angle to the transport direction of the printed-circuit board. The footprint must incorporate solder thieves downstream and at the side corners. During placement and before soldering, the package must be fixed with a droplet of adhesive. The adhesive can be applied by screen printing, pin transfer or syringe dispensing. The package can be soldered after the adhesive is cured. Typical dwell time of the leads in the wave ranges from 3 seconds to 4 seconds at 250 C or 265 C, depending on solder material applied, SnPb or Pb-free respectively. A mildly-activated flux will eliminate the need for removal of corrosive residues in most applications. 14.3.3 Manual soldering Fix the component by first soldering two diagonally-opposite end leads. Use a low voltage (24 V or less) soldering iron applied to the flat part of the lead. Contact time must be limited to 10 seconds at up to 300 C. When using a dedicated tool, all other leads can be soldered in one operation within 2 seconds to 5 seconds between 270 C and 320 C. 14.4 Package related soldering information Table 34. Mounting Through-hole mount Through-hole-surface mount Suitability of IC packages for wave, reflow and dipping soldering methods Package[1] CPGA, HCPGA DBS, DIP, HDIP, RDBS, SDIP, SIL PMFP[4] Soldering method Wave suitable suitable[3] not suitable Reflow[2] - - not suitable Dipping - suitable - LPC2917_19_1 (c) NXP B.V. 2007. All rights reserved. Preliminary data sheet Rev. 1.01 -- 15 November 2007 61 of 68 D R A FT NXP Semiconductors LPC2917/19 FT FT FT D D R R A A A FT FT FT D D R A FT D R R A FT D D D R A D R ARM9 microcontroller with CAN and LIN A D R A D R A D D R A FT A FT D R FT R Table 34. Mounting Suitability of IC packages for wave, reflow and dipping soldering methods ...continued Package[1] BGA, LBGA, LFBGA, SQFP, SSOP..T[5], TFBGA, VFBGA, XSON DHVQFN, HBCC, HBGA, HLQFP, HSO, HSOP, HSQFP, HSSON, HTQFP, HTSSOP, HVQFN, HVSON, SMS PLCC[7], SO, SOJ LQFP, QFP, TQFP SSOP, TSSOP, VSO, VSSOP CWQCCN..L[10], WQCCN..L[10] HTSSON..T[5], Soldering method Wave Reflow[2] suitable not suitable D R R - R A A Dipping A FT D R A FT D R A FT F FT Surface mount D D R A FT D not suitable[6] suitable - R A suitable not not recommended[7][8] recommended[9] suitable suitable suitable not suitable - - - - not suitable [1] [2] For more detailed information on the BGA packages refer to the (LF)BGA Application Note (AN01026); order a copy from your NXP Semiconductors sales office. All surface mount (SMD) packages are moisture sensitive. Depending upon the moisture content, the maximum temperature (with respect to time) and body size of the package, there is a risk that internal or external package cracks may occur due to vaporization of the moisture in them (the so called popcorn effect). For SDIP packages, the longitudinal axis must be parallel to the transport direction of the printed-circuit board. Hot bar soldering or manual soldering is suitable for PMFP packages. These transparent plastic packages are extremely sensitive to reflow soldering conditions and must on no account be processed through more than one soldering cycle or subjected to infrared reflow soldering with peak temperature exceeding 217 C 10 C measured in the atmosphere of the reflow oven. The package body peak temperature must be kept as low as possible. These packages are not suitable for wave soldering. On versions with the heatsink on the bottom side, the solder cannot penetrate between the printed-circuit board and the heatsink. On versions with the heatsink on the top side, the solder might be deposited on the heatsink surface. If wave soldering is considered, then the package must be placed at a 45 angle to the solder wave direction. The package footprint must incorporate solder thieves downstream and at the side corners. Wave soldering is suitable for LQFP, QFP and TQFP packages with a pitch (e) larger than 0.8 mm; it is definitely not suitable for packages with a pitch (e) equal to or smaller than 0.65 mm. Wave soldering is suitable for SSOP, TSSOP, VSO and VSSOP packages with a pitch (e) equal to or larger than 0.65 mm; it is definitely not suitable for packages with a pitch (e) equal to or smaller than 0.5 mm. [3] [4] [5] [6] [7] [8] [9] [10] Image sensor packages in principle should not be soldered. They are mounted in sockets or delivered pre-mounted on flex foil. However, the image sensor package can be mounted by the client on a flex foil by using a hot bar soldering process. The appropriate soldering profile can be provided on request. LPC2917_19_1 (c) NXP B.V. 2007. All rights reserved. Preliminary data sheet Rev. 1.01 -- 15 November 2007 62 of 68 D R A FT NXP Semiconductors LPC2917/19 FT FT FT D D R R A A A FT FT FT D D R A FT D R R A FT D D D R A D R ARM9 microcontroller with CAN and LIN A D R A D R A D D R A FT A FT D R FT R 15. Abbreviations Table 35. AHB BCL BDL CISC DTL SFSP SCL BEL CCO BIST RISC UART VPB Abbreviations list Description Advanced High-performance Bus Buffer Control List Buffer Descriptor List Complex Instruction Set Computers Device Transaction Level Abbreviation D R SCU Function Select Port x,y (use without the P if there are no x,y) Slot Control List Buffer Entry List Current Controlled Oscillator Built-In Self Test Reduced Instruction Set Computer Universal Asynchronous Receiver Transmitter VLSI Peripheral bus R A FT D R R A F D R A FT A FT A FT D R A D FT D R A LPC2917_19_1 (c) NXP B.V. 2007. All rights reserved. Preliminary data sheet Rev. 1.01 -- 15 November 2007 63 of 68 D R A FT NXP Semiconductors LPC2917/19 FT FT FT D D R R A A A FT FT FT D D R A FT D R R A FT D D D R A D R ARM9 microcontroller with CAN and LIN A D R A D R A D D R A FT A FT D R FT R 16. References [1] [2] [3] [4] [5] UM -- LPC2917/19 user manual ARM -- ARM web site D R ARM-SSP -- ARM primecell synchronous serial port (PL022) technical reference manual CAN -- ISO 11898-1: 2002 road vehicles - Controller Area Network (CAN) - part 1: data link layer and physical signalling LIN -- LIN specification package, revision 2.0 R A FT D R R A F D R A FT A FT A FT D R A D FT D R A LPC2917_19_1 (c) NXP B.V. 2007. All rights reserved. Preliminary data sheet Rev. 1.01 -- 15 November 2007 64 of 68 D R A FT NXP Semiconductors LPC2917/19 FT FT FT D D R R A A A FT FT FT D D R A FT D R R A FT D D D R A D R ARM9 microcontroller with CAN and LIN A D R A D R A D D R A FT A FT D R FT R 17. Revision history Table 36. Revision history Release date D R Supersedes LPC2915_17_19_1 R A FT D R R A F D R A FT A FT A FT D R A D FT * * Part LPC2915 removed Editorial updates Preliminary data sheet D R A 20070917 LPC2917_19_1 (c) NXP B.V. 2007. All rights reserved. Preliminary data sheet Rev. 1.01 -- 15 November 2007 65 of 68 D R A FT NXP Semiconductors LPC2917/19 FT FT FT D D R R A A A FT FT FT D D R A FT D R R A FT D D D R A D R ARM9 microcontroller with CAN and LIN A D R A D R A D D R A FT A FT D R FT R 18. Legal information 18.1 Data sheet status Document status[1][2] Objective [short] data sheet Preliminary [short] data sheet Product [short] data sheet [1] [2] [3] D R R A FT D R R A F D R A FT A FT A FT D R D Product status[3] Development Qualification Production Definition This document contains data from the objective specification for product development. This document contains data from the preliminary specification. This document contains the product specification. A FT D R A Please consult the most recently issued document before initiating or completing a design. The term `short data sheet' is explained in section "Definitions". The product status of device(s) described in this document may have changed since this document was published and may differ in case of multiple devices. The latest product status information is available on the Internet at URL http://www.nxp.com. 18.2 Definitions Draft -- The document is a draft version only. The content is still under internal review and subject to formal approval, which may result in modifications or additions. NXP Semiconductors does not give any representations or warranties as to the accuracy or completeness of information included herein and shall have no liability for the consequences of use of such information. Short data sheet -- A short data sheet is an extract from a full data sheet with the same product type number(s) and title. A short data sheet is intended for quick reference only and should not be relied upon to contain detailed and full information. For detailed and full information see the relevant full data sheet, which is available on request via the local NXP Semiconductors sales office. In case of any inconsistency or conflict with the short data sheet, the full data sheet shall prevail. result in personal injury, death or severe property or environmental damage. NXP Semiconductors accepts no liability for inclusion and/or use of NXP Semiconductors products in such equipment or applications and therefore such inclusion and/or use is at the customer's own risk. Applications -- Applications that are described herein for any of these products are for illustrative purposes only. NXP Semiconductors makes no representation or warranty that such applications will be suitable for the specified use without further testing or modification. Limiting values -- Stress above one or more limiting values (as defined in the Absolute Maximum Ratings System of IEC 60134) may cause permanent damage to the device. Limiting values are stress ratings only and operation of the device at these or any other conditions above those given in the Characteristics sections of this document is not implied. Exposure to limiting values for extended periods may affect device reliability. Terms and conditions of sale -- NXP Semiconductors products are sold subject to the general terms and conditions of commercial sale, as published at http://www.nxp.com/profile/terms, including those pertaining to warranty, intellectual property rights infringement and limitation of liability, unless explicitly otherwise agreed to in writing by NXP Semiconductors. In case of any inconsistency or conflict between information in this document and such terms and conditions, the latter will prevail. No offer to sell or license -- Nothing in this document may be interpreted or construed as an offer to sell products that is open for acceptance or the grant, conveyance or implication of any license under any copyrights, patents or other industrial or intellectual property rights. 18.3 Disclaimers General -- Information in this document is believed to be accurate and reliable. However, NXP Semiconductors does not give any representations or warranties, expressed or implied, as to the accuracy or completeness of such information and shall have no liability for the consequences of use of such information. Right to make changes -- NXP Semiconductors reserves the right to make changes to information published in this document, including without limitation specifications and product descriptions, at any time and without notice. This document supersedes and replaces all information supplied prior to the publication hereof. Suitability for use -- NXP Semiconductors products are not designed, authorized or warranted to be suitable for use in medical, military, aircraft, space or life support equipment, nor in applications where failure or malfunction of a NXP Semiconductors product can reasonably be expected to 18.4 Trademarks Notice: All referenced brands, product names, service names and trademarks are the property of their respective owners. I2C-bus -- logo is a trademark of NXP B.V. 19. Contact information For additional information, please visit: http://www.nxp.com For sales office addresses, send an email to: salesaddresses@nxp.com LPC2917_19_1 (c) NXP B.V. 2007. All rights reserved. Preliminary data sheet Rev. 1.01 -- 15 November 2007 66 of 68 D R A FT NXP Semiconductors LPC2917/19 FT FT FT D D R R A A A FT FT FT D D R A FT D R R A FT D D D R A D R ARM9 microcontroller with CAN and LIN A D R A D R A D D R A FT A FT D R FT R 20. Contents 1 1.1 1.2 2 2.1 2.2 2.3 2.4 3 3.1 4 4.1 5 6 6.1 6.2 6.2.1 6.2.2 7 7.1 7.1.1 7.1.2 7.1.3 7.1.4 7.2 7.2.1 7.2.2 8 8.1 8.1.1 8.1.2 8.1.3 8.1.4 8.1.5 8.1.6 8.2 8.2.1 8.2.2 8.2.3 8.2.4 8.2.5 8.3 8.3.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 About this document . . . . . . . . . . . . . . . . . . . . . 1 Intended audience . . . . . . . . . . . . . . . . . . . . . . 1 General description . . . . . . . . . . . . . . . . . . . . . . 1 Architectural overview . . . . . . . . . . . . . . . . . . . 1 ARM968E-S processor . . . . . . . . . . . . . . . . . . . 2 On-chip flash memory system . . . . . . . . . . . . . 2 On-chip static RAM. . . . . . . . . . . . . . . . . . . . . . 3 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 General . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 Ordering information . . . . . . . . . . . . . . . . . . . . . 4 Ordering options . . . . . . . . . . . . . . . . . . . . . . . . 4 Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . 5 Pinning information . . . . . . . . . . . . . . . . . . . . . . 6 Pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 Pin description . . . . . . . . . . . . . . . . . . . . . . . . . 6 General description . . . . . . . . . . . . . . . . . . . . . 6 LQFP144 pin assignment . . . . . . . . . . . . . . . . . 6 Functional description . . . . . . . . . . . . . . . . . . 10 Reset, debug, test and power description . . . 10 Reset and power-up behavior . . . . . . . . . . . . 10 Reset strategy . . . . . . . . . . . . . . . . . . . . . . . . 10 IEEE 1149.1 interface pins (JTAG boundary-scan test). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 Power supply pins description . . . . . . . . . . . . 11 Clocking strategy . . . . . . . . . . . . . . . . . . . . . . 11 Clock architecture . . . . . . . . . . . . . . . . . . . . . . 11 Base clock and branch clock relationship. . . . 13 Block description. . . . . . . . . . . . . . . . . . . . . . . 14 Flash memory controller . . . . . . . . . . . . . . . . . 14 Overview. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 Description . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 Flash memory controller pin description . . . . . 16 Flash memory controller clock description . . . 16 Flash layout . . . . . . . . . . . . . . . . . . . . . . . . . . 16 Flash bridge wait-states . . . . . . . . . . . . . . . . . 17 External static memory controller . . . . . . . . . . 18 Overview. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 Description . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 External static-memory controller pin description . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 External static-memory controller clock description . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 External memory timing diagrams . . . . . . . . . 19 General subsystem. . . . . . . . . . . . . . . . . . . . . 22 General subsystem clock description . . . . . . . 22 8.3.2 8.3.2.1 8.3.2.2 8.3.2.3 8.3.3 8.3.3.1 8.3.3.2 8.3.3.3 8.3.4 8.3.4.1 8.3.4.2 8.3.4.3 8.4 8.4.1 8.4.2 8.4.2.1 8.4.2.2 8.4.2.3 8.4.2.4 8.4.3 8.4.3.1 8.4.3.2 8.4.3.3 8.4.3.4 8.4.4 8.4.4.1 8.4.4.2 8.4.4.3 8.4.4.4 8.4.5 8.4.5.1 8.4.5.2 8.4.5.3 8.4.5.4 8.4.5.5 8.4.6 8.4.6.1 8.4.6.2 8.4.6.3 8.4.6.4 8.5 8.5.1 8.5.2 8.5.3 8.6 8.6.1 8.6.2 D R Chip and feature identification . . . . . . . . . . . . Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . Description . . . . . . . . . . . . . . . . . . . . . . . . . . . CFID pin description . . . . . . . . . . . . . . . . . . . System Control Unit (SCU) . . . . . . . . . . . . . . Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . Description . . . . . . . . . . . . . . . . . . . . . . . . . . . SCU pin description . . . . . . . . . . . . . . . . . . . . Event router . . . . . . . . . . . . . . . . . . . . . . . . . . Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . Description . . . . . . . . . . . . . . . . . . . . . . . . . . . Event-router pin description and mapping to register bit positions . . . . . . . . . . . . . . . . . . . . Peripheral subsystem . . . . . . . . . . . . . . . . . . Peripheral subsystem clock description. . . . . Watchdog timer . . . . . . . . . . . . . . . . . . . . . . . Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . Description . . . . . . . . . . . . . . . . . . . . . . . . . . . Pin description . . . . . . . . . . . . . . . . . . . . . . . . Watchdog timer clock description . . . . . . . . . Timer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . Description . . . . . . . . . . . . . . . . . . . . . . . . . . . Pin description . . . . . . . . . . . . . . . . . . . . . . . . Timer clock description . . . . . . . . . . . . . . . . . UARTs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . Description . . . . . . . . . . . . . . . . . . . . . . . . . . . UART pin description . . . . . . . . . . . . . . . . . . . UART clock description . . . . . . . . . . . . . . . . . Serial peripheral interface . . . . . . . . . . . . . . . Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . Functional description . . . . . . . . . . . . . . . . . . Modes of operation . . . . . . . . . . . . . . . . . . . . SPI pin description . . . . . . . . . . . . . . . . . . . . . SPI clock description . . . . . . . . . . . . . . . . . . . General-purpose I/O . . . . . . . . . . . . . . . . . . . Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . Description . . . . . . . . . . . . . . . . . . . . . . . . . . . GPIO pin description . . . . . . . . . . . . . . . . . . . GPIO clock description . . . . . . . . . . . . . . . . . CAN gateway . . . . . . . . . . . . . . . . . . . . . . . . . Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . Global acceptance filter . . . . . . . . . . . . . . . . . CAN pin description . . . . . . . . . . . . . . . . . . . . LIN . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . LIN pin description . . . . . . . . . . . . . . . . . . . . . continued >> R A FT D R R A F D R A FT D FT D R A A FT 22 22 22 22 22 22 22 22 22 22 23 A FT D 23 23 23 24 24 24 24 24 24 24 25 25 26 26 26 26 26 27 27 27 27 28 28 28 29 29 29 29 29 30 30 30 30 30 30 31 R A LPC2917_19_1 (c) NXP B.V. 2007. All rights reserved. Preliminary data sheet Rev. 1.01 -- 15 November 2007 67 of 68 D R A FT NXP Semiconductors LPC2917/19 FT FT FT D D R R A A A FT FT FT D D R A FT D R R A FT 58 59 59 59 59 59 59 59 60 61 61 63 64 65 66 66 66 66 66 67 68 D R A D R ARM9 microcontroller with CAN and LIN A D R A D R A D D R A FT A FT D R FT R 8.7 8.7.1 8.7.2 8.7.2.1 8.7.3 8.7.4 8.7.5 8.7.5.1 8.7.5.2 8.7.5.3 8.7.5.4 8.7.6 8.7.6.1 8.7.6.2 8.7.6.3 8.7.6.4 8.7.6.5 8.7.6.6 8.7.7 8.7.7.1 8.7.7.2 8.7.7.3 8.7.7.4 8.8 8.8.1 8.8.2 8.8.3 8.8.4 8.8.4.1 8.8.4.2 8.8.4.3 8.8.4.4 8.8.5 8.8.5.1 8.8.5.2 8.8.5.3 8.8.6 8.8.6.1 8.8.6.2 8.8.6.3 8.9 8.9.1 8.9.2 8.9.3 8.9.4 9 10 11 12 Modulation and sampling control subsystem . Overview. . . . . . . . . . . . . . . . . . . . . . . . . . . . . Description . . . . . . . . . . . . . . . . . . . . . . . . . . . Synchronization and trigger features of the MSCSS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . MSCSS pin description. . . . . . . . . . . . . . . . . . MSCSS clock description . . . . . . . . . . . . . . . . Analog-to-digital converter . . . . . . . . . . . . . . . Overview. . . . . . . . . . . . . . . . . . . . . . . . . . . . . Description . . . . . . . . . . . . . . . . . . . . . . . . . . . ADC pin description . . . . . . . . . . . . . . . . . . . . ADC clock description . . . . . . . . . . . . . . . . . . PWM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Overview. . . . . . . . . . . . . . . . . . . . . . . . . . . . . Description . . . . . . . . . . . . . . . . . . . . . . . . . . . Synchronizing the PWM counters. . . . . . . . . . Master and slave mode . . . . . . . . . . . . . . . . . PWM pin description. . . . . . . . . . . . . . . . . . . . PWM clock description . . . . . . . . . . . . . . . . . . Timers in the MSCSS . . . . . . . . . . . . . . . . . . . Overview. . . . . . . . . . . . . . . . . . . . . . . . . . . . . Description . . . . . . . . . . . . . . . . . . . . . . . . . . . MSCSS timer-pin description . . . . . . . . . . . . . MSCSS timer-clock description . . . . . . . . . . . Power, clock and reset control subsystem . . . Overview. . . . . . . . . . . . . . . . . . . . . . . . . . . . . Description . . . . . . . . . . . . . . . . . . . . . . . . . . . PCR subsystem clock description . . . . . . . . . Clock Generation Unit (CGU) . . . . . . . . . . . . . Overview. . . . . . . . . . . . . . . . . . . . . . . . . . . . . Description . . . . . . . . . . . . . . . . . . . . . . . . . . . PLL functional description . . . . . . . . . . . . . . . CGU pin description . . . . . . . . . . . . . . . . . . . . Reset Generation Unit (RGU). . . . . . . . . . . . . Overview. . . . . . . . . . . . . . . . . . . . . . . . . . . . . Description . . . . . . . . . . . . . . . . . . . . . . . . . . . RGU pin description . . . . . . . . . . . . . . . . . . . . Power Management Unit (PMU). . . . . . . . . . . Overview. . . . . . . . . . . . . . . . . . . . . . . . . . . . . Description . . . . . . . . . . . . . . . . . . . . . . . . . . . PMU pin description . . . . . . . . . . . . . . . . . . . . Vectored interrupt controller . . . . . . . . . . . . . . Overview. . . . . . . . . . . . . . . . . . . . . . . . . . . . . Description . . . . . . . . . . . . . . . . . . . . . . . . . . . VIC pin description . . . . . . . . . . . . . . . . . . . . . VIC clock description . . . . . . . . . . . . . . . . . . . Limiting values. . . . . . . . . . . . . . . . . . . . . . . . . Thermal characteristics . . . . . . . . . . . . . . . . . Static characteristics. . . . . . . . . . . . . . . . . . . . Dynamic characteristics . . . . . . . . . . . . . . . . . 31 31 31 32 34 34 35 35 35 36 37 37 37 37 38 39 39 39 40 40 40 40 40 40 40 40 41 41 41 42 45 46 47 47 47 48 48 48 48 50 50 50 50 51 51 51 52 53 55 13 14 14.1 14.2 14.2.1 14.2.2 14.3 14.3.1 14.3.2 14.3.3 14.4 15 16 17 18 18.1 18.2 18.3 18.4 19 20 Package outline. . . . . . . . . . . . . . . . . . . . . . . . Soldering . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . Through-hole mount packages . . . . . . . . . . . Soldering by dipping or by solder wave . . . . . Manual soldering . . . . . . . . . . . . . . . . . . . . . . Surface mount packages . . . . . . . . . . . . . . . . Reflow soldering . . . . . . . . . . . . . . . . . . . . . . Wave soldering . . . . . . . . . . . . . . . . . . . . . . . Manual soldering . . . . . . . . . . . . . . . . . . . . . . Package related soldering information. . . . . . Abbreviations . . . . . . . . . . . . . . . . . . . . . . . . . References. . . . . . . . . . . . . . . . . . . . . . . . . . . . Revision history . . . . . . . . . . . . . . . . . . . . . . . Legal information . . . . . . . . . . . . . . . . . . . . . . Data sheet status . . . . . . . . . . . . . . . . . . . . . . Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . Disclaimers . . . . . . . . . . . . . . . . . . . . . . . . . . Trademarks . . . . . . . . . . . . . . . . . . . . . . . . . . Contact information . . . . . . . . . . . . . . . . . . . . Contents. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . D Please be aware that important notices concerning this document and the product(s) described herein, have been included in section `Legal information'. D D R R R A A A FT D F FT D D R R A A FT D FT D R A FT R A (c) NXP B.V. 2007. All rights reserved. For more information, please visit: http://www.nxp.com For sales office addresses, please send an email to: salesaddresses@nxp.com Date of release: 15 November 2007 Document identifier: LPC2917_19_1 |
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